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Cyclone Eval Board Schematics |
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Cyclone Schematics, 80960KX Module |
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Cyclone Schematics, Squall Ethernet Module |
| RP |
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Cyclone Schematics, Squall Ethernet Module |
| SX |
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Cyclone Eval Board Schematics |
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Cyclone Eval Board Schematics |
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Cyclone Schematics, 80960SX Module |
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Cyclone Schematics, Squall Ethernet Module |
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EV80960SX Schematics Rev 1.1 in Orcad Fo |
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Schematics in Postscript Format |
| Not Categorized |
|
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80960RP Schematics |
| Software Support |
| All |
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Helpful Hint: Optimizing Switch Statements For Execution Performance In iC960 R3.0 And R3.5 |
| CX |
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80960CA Code Examples |
|
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80960CA Detect Util for A28 DMA |
|
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80960CX Tomcat Pld Source Files |
|
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82596 Ethernet Drivers for the 960CA |
|
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Cyclone EP Example Program Install |
|
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EPS Files |
|
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EV80960CA CADIC Jedec PAL File |
|
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EV80960CA Eval Board Jedec Files |
|
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EV80960CA PAL Source Codes |
|
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EV80960CA U5 4Meg Jedec File |
|
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i960® CA/CF Microprocessors's Self Test |
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Monitor Used to Talk to Eval Board |
|
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Monitor Used to Talk to Eval Board |
|
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Procedures Required to Write ISRs |
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The 80960 QUICKval Kit |
|
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Writing Leaf Procedures With ASM960 That Can Be Called From C960 Programs |
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[IBIS]80960CA(16,25,33)/80960CF(16,25) |
|
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[IBIS]80960CA(16,25,33)/80960CF(16,25) 1 |
|
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[IBIS]80960CF (33 MHz) 196L PQFP |
|
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[IBIS]80960CF (33MHz) 168L PGA |
|
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[SRC] 80960 Software Examples |
|
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[TXT] Init Code For the 80960CS in Assembly |
| HX |
|
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BSDL File for the 80960Hx 168 Pin PGA |
|
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BSDL File for the 80960Hx 208 Pin PQ2 (PQFP) |
|
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Cyclone EP Example Program Install |
|
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EPS Files |
|
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The 80960 QUICKval Kit |
|
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[IBIS] 80960Hx 168L PGA |
|
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[IBIS] 80960Hx 208L PQ2 |
| JX |
|
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80960JX Startup Code |
|
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80L960JA/JF (16,25,33MHz) 132 PQFP |
|
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BSDL File for the 80960JX 132 Pin PGA 14 |
|
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BSDL File for the 80960JX 132 Pin PQFP p |
|
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Cyclone EP Example Program Install |
|
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EPS Files |
|
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JX DRAM Design Info For AP-712 |
|
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Monitor Used to Talk to Eval Board |
|
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Monitor Used to Talk to Eval Board |
|
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The 80960 QUICKval Kit |
|
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[IBIS]80960JA/JD/JF (16,25,33,40,44,50) |
|
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[IBIS]80960JA/JD/JF (16,25,33,40,44,50) |
|
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[IBIS]80960JA/JF (16,25,33MHz) 132 PGA |
|
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[SRC] 80960 Software Examples |
| KX |
|
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Cyclone EP Example Program Install |
|
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EPS Files |
|
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Implementation of Elements for 80960 KA/KB |
|
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The 80960 QUICKval Kit |
|
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The 80960 QUICKval kit .exe file |
| RP |
|
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The 80960 QUICKval Kit |
| SX |
|
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Cyclone EP Example Program Install |
|
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EPS Files |
|
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EV80960SX JEDEC Files for Rev 1.1 |
|
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Pal Source Code in ABL Format. Rev 1.1 |
|
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PLD Equ. for Laser Printer Controller |
|
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The 80960 QUICKval Kit |
|
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[IBIS]80960SA (10,16,20MHz) 84L PLCC |
|
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[IBIS]80960SA (10.16,20MHz) 80L QFP |
|
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[IBIS]80960SB (10,16MHz) 34L PLCC |
|
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[IBIS]80960SB (10,16MHz) 80L QFP |
| Spec Updates |
| CX |
|
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SU-27287501 80960CA/CF Specification Update |
| HX |
|
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SU-27283002 80960HA/HD/HT Specification Update |
| JX |
|
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SU-27285201 80960JA/JF/JD Specification Update |
| KX |
|
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SU-27285101 80960KA/KB Specification Update |
| MX |
|
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SU-27286801 80960MX Specification Update |
| SX |
|
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SU-27285001 80960SA/SB Specification Update |
| Not Categorized |
|
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80960Rx Specification Update |
| Technical Notes |
| All |
|
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80960 Technical Notes |
|
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i960(R) Embedded Microprocessor Q & A |
|
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i960(R) Thermal Fundamentals |
|
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Installing The EVA960KB Board In Intel386(TM) And Intel486(TM) |
|
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Synchronizing the 80960CA in Multi-Processor Systems |
| CX |
|
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Big-Endian Programming Using i960(R) Processors |
| HX |
|
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Interfacing the Byte-Wide SmartVoltage FlashFile(TM) Memory Family to the Intel960® Microprocessor Family |
|
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Reduced Power Options for the 80960HA/HD/HT Processor |
| JX |
|
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Converting System Designs from i960(R)CX Processors to i960(R)JX Processors |
|
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Creating Cacheable Contiguous Memory Partitions on the 80960JX Using Logical Memory Control Registers (LMCONs) |
|
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Easy upgrade from the 80960KX to the 80960JX |
|
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Interfacing the Byte-Wide SmartVoltage FlashFile(TM) Memory Family to the Intel960® Microprocessor Family |
|
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JTAG Modification Instructions for the Jx Processor Module from Cyclone Microsystems |
|
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Possible Erratic Power-up Behavior on the i960(R)JX Processor Due to Improperly Initialized JTAG TAP Controller |
|
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Upgrading System Designs from i960(R)KX Processors to i960(R)JX Processors |
| RP |
|
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Interfacing the Byte-Wide SmartVoltage FlashFile(TM) Memory Family to the Intel960® Microprocessor Family |
| Not Categorized |
|
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IC960 R3.5 New Feature (-Gds) Simplifies Assignment of Global Data to Memory |
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