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With the recent introduction of Intels Cobra family of i960(R) Jx processors, conversion from other 80960 family members is evident. If your present system or companion chip is based on the i960(R) Cx processor and you anticipate converting to 80960JA/JD/JF processors in the future, you can plan for that transition by observing suggestions in this technical note.
This document describes the hardware and software differences between 80960Jx and 80960Cx processors that will need to be compensated for in a conversion. This document will not list in detail all of the differences between the JX and the CX, or the added features. For more detailed information on both processors please refer to the following:
Electrical specifications for these products are found in the following documents:
· 80960 JA/JF Embedded 32-Bit Processor Data Sheet, Order #272504
· 80960CA-33, -25, -16 32-Bit High-Performance Embedded Processor Data Sheet, Order #270727
· 80960CF-40 32-Bit High-Performance Superscalar Processor Data Sheet, Order #272493
· 80960CF-33, -25, -16 32-Bit High-Performance Superscalar Processor Data Sheet, Order #272187
Functional descriptions for these products are found in the following documents:
· i960(R) Jx Microprocessor Users Manual, Order #272483
· i960(R) Cx Microprocessor Users Manual, Order #270710
Unlike the 80960CA/CF processors which have separate address and data busses, the 80960Jx devices have a 32-bit, multiplexed address/data bus. Both the Cx and the Jx processor busses are capable of high bandwidth burst transfers, although the i960Jx does not have bus pipelining capability. The 80960Jx products do not occupy the same PQFP and PGA packages as the 80960Cx products, nor are they pin-compatible.
The following list identifies some of the control signals that are directly compatible to their 80960Cx counterparts:
· The BREQ# pin on the 80960Cx is not included on the 80960Jx, however a similar function is provided by the new BSTAT pin. The BSTAT pin indicates that the processor may soon stall unless it gains sufficient access to the bus.
· WIDTH/HLTD1:0 pins denote the programmed bus width corresponding to each bus access and can also indicate if the processor is halted.
· The 80960Jx supports boundary scan testing and includes five new pins for the implementation of this function: TCK, TDI, TDO, TRST#, TMS.
· The WAIT# and DMA# pins were left off because they were supporting the internal wait state generator and the DMA unit respectively, which were not included on the 80960Jx.
The HOLD/HOLDA protocol provides that the i960Jx processor cannot pass directly from a Td bus state to the Th (HOLD) bus state without passing through the Tr state(s). This is necessary to support the RDYRCV# pin described previously. The timing relations hip of the HOLD and HOLDA pins will be unchanged.
On the 80960Cx, the LOCK# pin signals that a read/modify/write (atomic) sequence is in progress, but a secondary bus-master may still put a hold on the bus, using HOLD, before the write portion of the sequence has occurred. The 80960Jx differs in that it will prevent a secondary bus-master from holding the bus until the write cycle of the sequence has occurred. In addition, on the 80960Cx the BOFF# signal can prevent the write cycle of the read/modify/write sequence from ever occurring. The 80960Jx does n ot have a BOFF# pin.
The 80960Jx processor's interrupt control unit is identical to that of the i960CA/CF processors. It has eight general purpose XINT# interrupt pins and one NMI# pin. These are active-low inputs, but unlike the i960CA/CF which latches interrupts on the fall ing edge of PCLK, the 80960Jx interrupt pins will be sampled on the rising edge of CLKIN.
The i960Jx processor does not have a DMA unit. If your i960Cx design uses DMA, reevaluate that need. In some cases, car efully written assembly code loops will perform as well as the 80960Cx DMA controller. If a DMA controller is critical to your 80960Jx-based design, Intel recommends that you design a DMA controller in a gate array or other external logic.
The LOCK# pin on the 80960Jx is tested upon RESET# deassertion. If it is low, the processor will enter the ONCE three-state test mode. The 80960Cx processor has a separate pin (ONCE#) for invoking ONCE mode.
All versions of the Jx processor will be clocked at the bus frequency (CLKIN), even if the core clock is doubled (80960JD). The i960Cx processor can be clocked at either 1X or 2X the bus frequency (PCLK).
Unlike the 80960Cx, the 80960Jx does not contain an internal wait state generator.
The location of the Initialization Boot Record is different on the JX and the CX. The IBR on the CX is located at 0xFFFFFF00, while the IBR for the JX is at 0xFEFFFF30. On the JX, the are a where the CX IBR is located is reserved, however on the CX the area where the JX boot code is located is external user memory.
The formats of the IBRs for these processors are also slightly different. The first four words of the IBR on the CX each contain a byte of MCON0 and on the JX they each contain a byte of PMCON14_15.
A number characterizing both the microprocessor type and stepping is placed in g0 on reset for both the JX and the CX. In addition, this device ID is also placed in a memory-mapped register on the JX and can be accessed directly.
The initialization code used on the CX is almost completely compatible with the JX. The structures of the interrupt table, the fault table, and the system procedure table are completely compatible. The differences include the following:
· The Register Cache Configuration Word in the PRCB indicates the number of cached register sets on the Cx, but on the Jx it indicates the number of free frames to be used by non-critical code.
· The ICON register in the control table includes a DMA bit on the Cx. This bit is reserved on the Jx.
· The physical memory region configuration words in the control table are set up slightly different. The Cx has 16 MCON registers, while the JX has only 8 PMCON registers which have a reserved word after each.
Sample initialization code is available for both the Jx and the Cx in their respective manuals.
The number of programmable memory regions available on the Cx is 16, w hile the number of regions on the Jx is 8. The two processors take a slightly different approach to programming these regions. The Cx uses 16 MCON registers which control among other things, bus width, byte ordering, and data cache enabling for the region . The Jx contains 8 PMCON registers for programming bus width for the physical memory regions. It also uses 2 types of logical templates each comprised of 2 logical memory control registers (LMMRs and LMADR s) to control data cache enabling for its specifi c region. The Jx has a default logical memory configuration register (DLMCON) for accesses that do not fall inside one of the two logical memory templates. DLMCON also controls byte ordering for the entire memory map.
The control tables for the JX and CX have several differences including location of the breakpoint registers, and PMCONs on the JX versus MCON s on the Cx. After initialization, if any changes to the control table need to be made different procedures can be used: CX uses sysctl, JX uses sysctl or direct changes to the memory mapped registers.
Cache Initialization for the most part is the same between the two processors:
· The instruction cache can be invalidated, enabled, and disabled the same way on the JX and the CX using sysctl.
· The data cache enabling and disabling bits are contained in the control tables, and need to be dealt with differently for each processor.
· The new instruction cache and data cache control instructions on the JX are not compatible with the CX.
Not all registers on the JX will contain the same initial values, as their counterpart on the CX. Some of these registers include PC, IPB0, IPB1, DAB0, DAB1, BPCON. The user should take care to initialize all registers on each part before using them.
Procedure calls and related table structures are entirely compatible.
The software handling of interrupts including related table structures and procedures is compatible with the following exceptions: IPND and IMSK are special function registers on the CX, and they are memory mapped registers on the JX.
The software handling of faults including related table structures and procedures is entirely compatible.
There are no major tracing and debugging differences between the JX and the CX. One minor difference is in the breakpoint registers. Application code on the Jx must always first request and acquire modification rights to the hardware breakpoint resources (BPCONs) before any attempt is made to modify them. This procedure is not required on the Cx.
New instructions on the JX (designated in the i960(R) Jx Microprocessor Users Manual) are not compatible with the CX.
Branch Prediction is not supported on the JX. The JX will ignore the branch prediction bit in code that is compiled with it.
Special Function Registers are not supported on the JX.
The instruction cache on the JA is 2K while the JF and JD are 4K as is the CF. The instruction cache on the CA is only 1K.
The data cache on the CF is 1K as is the JA. While the JF and JD have 2K of data cache. All are direct mapped. The cache size increase on the JF and JD may be useful to an application that is only enabling data caching in a section of memory that is the s ame size or smaller than the data cache, which would insure that critical data can never be pre-empted from the cache by other data that maps to the same location. Now the application can enable twice as much memory for data caching.
The data RAM is 1K for both the CX and the JX.
The JX has 8 fixed sets of local registers, and can reserve between 0 and 7 sets for high priority interrupts. The CX can vary the number of local register sets it uses from 0 up to 16. Both the JX and the CX use the Register Cache Configuration Word in t he PRCB to program local register availability.
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