Synchronizing the 80960CA in Multi-Processor Systems

In a multi-processor system design, it is often necessary to ensure that clocking schemes of all of the processors in the system are consistent. When a multi-processor system is constructed with two or more i960 CA processors, the output clocks (PCLK2:1) of each processor need to be synchronized. Synchronizing the output clocks accommodates communication or memory sharing between the processors.

Synchronizing the PLCK2:1 signals for each processors is accomplished by providing a common input clock (CLKIN) signal for each processor in the system, and by aligning the deassertion (rising) edge of the RESET# signal appropriately with the input clock.

The i960 CA processor is configured in 1X or 2X input mode, based on the value of the CLKMODE pin. The 80960CA Data Sheet explains these clock modes in detail. In the 1X input mode, the CLKIN signal is phase locked to the system clock outputs (PCLK2:1). The CLKIN to PCLK2:1 delay is small (on the order of +/- 1 to 2 ns). The CLKIN to PCLK2:1 skew for 2X clock mode is a wider range, since CLKIN and PCLK2:1 are not phase locked in this mode. The relative skew between PLCK2:1 signals for each processor, in the worst case, is the difference between max and min clock skews. It is more useful to use the 1X clock mode to synchronize the output clocks, since the input-to-output clock skew is small in this mode.

Figure A shows the processor reset in the 2X clock mode. The RESET# signal is sampled inactive (high) on the falling edge of CLKIN. The PCLK2:1 signals are driven high until the third rising edge of CLKIN following the inactive RESET#. Case 1 and 2 show the PCLK2:1 in two different phases at the rising edge of the RESET# signal. The tis4 and tih4 parameters are provided in the 80960CA Data Sheet.

Figure B shows the processor reset in the 1X clock mode. In the 1X clock mode, the RESET# signal is sampled inactive (high) when the CLKIN signal is high. The PCLK2:1 signals are then driven high until the second falling edge of CLKIN following the rising edge of RESET#. The rising edge of RESET# is referenced to the falling edge of a 2X system clock which is half the frequency and synchronous to the CLKIN signal. The parameters tisx and tihx will be determined with future investigations.