Possible Erratic Power-up Behavior on the i960(R)JX Processor Due to Improperly Initialized JTAG TAP Controller

Revision 1.0

The i960(R) Jx processor is the first generation of the 80960 family to incorporate JTAG Boun dary Scan. While the JX JTAG unit is fully IEEE 1149.1 compliant, it may cause unpredictable behavior at the processors system pins if it is not correctly initialized.
When improperly initialized, the TAP controller may intermittently power up with the EXTEST (boundary scan) instruction selected, which may cause the processor to drive random values out the system pins (e.g. AD bus, ADS#, BLAST#) from boundary scan cells . If the system does not provide proper initialization to the JTAG unit, the processo r may randomly power-up in boundary scan mode, in which case the processor would not execute code. When this happens, the designer may observe inexplicable values on the pins such as HOLDA being asserted when HOLD is de-asserted (can never happen during normal operation).
The current JTAG TAP controller implementation does not have an automatic power-up reset circuit to place the TAP controller in a known state. Furthermore, the IEEE1149.1 standard prohibits a JTAG design from using a system reset pin ( such as RESET#) to initialize the TAP controller. Therefore, it is up to the system designer to assure that the TAP controller is initialized properly. The TAP controller must be initialized regardless of whether the JTAG port is used or not. This is a ccomplished in either of two ways:

For system designs that never plan to use the JTAG portion of the JX processor, the designer should simply connect the TRST# input to ground. TMS, TDI, and TCK should be pulled high with a 10k resistor. TDO should be left floating.

For system designs that do use JTAG, but do not apply a clock to TCK during normal operation , the designer should connect a pulldown resistor to the TRST# pin. A value of 2.7k is sufficiently small to assure that TRST# is pulled to a logic 0 (pulls against TRST# internal pullup), but large enough to be overdriven by automatic test equipment during test or debug. The designer should assure that TMS, TDI, and TCK are either pulled up or driven high during normal operation.

For system designs that do use JTAG, and apply a clock to TCK during normal operation , the designer should assure that TMS and TDI are pulled up or driven high during normal operation. TRST# does not have to be pulled low, but it would be safer to do so, in case future revisions of the design shut off TCK during normal operation.