Upgrading System Designs from i960(R)KX Processors to i960(R)JX Processors

• Hardware Considerations
  • Bus Organization
  • Control Signals
  • Bus Arbitration
  • Interrupt Control Inputs
  • Other Hardware Compatibility Notes
• Software Considerations
  • IBR-Initialization Boot Record
  • Device ID
  • Initialization Code
  • Register Values after Reset/Reinitialization
  • Procedure Calls
  • Interrupts
  • Memory Control
  • IACs
  • Faults
  • Tracing and Debugging
  • Instructions
  • Floating Point
  • Data RAM, Local Registers, and MMRs
  • Caches
  • Other Compatibility Notes
• Index

January 3, 1995

Revision 2.1

Intels new Cobra family of i960Ò Jx processors is here. Intel intends the 80960Jx products to be an easy upgrade choice from t he existing 80960KA/KB microprocessor and paid special attention to bus and control signal compatibility during the design process. If your present system or companion chip is based on the 80960KA/KB processor and you anticipate upgrading to the 80960JA/J D/JF processors in the future, you can plan for that transition by observing suggestions in this technical note.

This document describes the hardware and software differences between the two processors that will need to be compensated for in upgrading. This document will not list in detail all of the differences between the 80960Jx and the 80960Kx, or the added features. For more detailed information on both processors please refer to the following:

Electrical specifications for these products are found in the following documents:

· 80960 JA/JF Embedded 32-Bit Processor Data Sheet, Order #272504

· 80960KA Embedded 32-Bit Microprocessor Data Sheet, Order #270775

· 80960KB Embedded 32-Bit Microprocessor with Integrated Floating-Point Unit Data Sheet, Order #270565

Functional descriptions for these products are found in the following documents:

· i960Ò Jx Microprocessor User s Manual, Order #272483

· i960Ò KA/KB Microprocessor Programmers Reference Manual, Order #270567

· i960Ò KB Hardware Designers Reference Manual, Order #270564

Hardware Considerations

Bus Organization

Like the 80960KA/KB processor, the 80960Jx devices have a 32-bit, multiplexed address/data bus ca pable of high bandwidth burst transfers. Although the 80960Jx products will occupy the same 132-lead PQFP and PGA packages and have similar control signals, they are not pin-compatible to the existing 80960KA/KB device.

Enhancements to the bus include demultiplexed, incrementing address signals A3:2 and programmable bus width. For 16-bit buses, the processor will drive address signal A1 on the BE1# pin. For 8-bit buses, the processor will also drive address signal A0 on the BE0# pin. This addressing convention corresponds to the 80960Cx processors.

Control Signals

The new microprocessor uses three-state output buffers instead of open-drain buffers for all control signal outputs. This change could affect a few existing 80960Kx designs that have multiple processors sharing a memory subsystem.

The following list identifies control signals that are directly compatible to their 80960KA/KB counterparts:

· During the address cycle, pins AD1:0 denote SIZE bits to indicate the length of a burst. The functionality of these pins is now extended to 8- and 16- bit bus widths, where the maximum number of transfers is also four.

· ALE# works identically. For new design work, the complementary ALE signal is available also.

· Byte enables BE3:0# on the 80960Kx processor are valid at least one clock before the corresponding data state of a burst. Byte enables may change states during a burst access to qualify unaligned data transfers. In other words, the byte enables are pipelined and toggling and external system logic must latch the signals.

Microcode in the 80960Jx processors breaks up requests for unaligned data into smaller bus accesses which will always be individually aligned. The new processors drive appropriate BE3:0# pins active during Ta and inactive during Tr. The pins do not toggl e within the burst, so there is no need to latch them. Existing system logic designed for pipelined, toggling byte enables will automatically handle the new BE3:0# signals as a trivial case.

· W/R#, DT/R# and DEN# pins function identically.

· The new processor asserts ADS# only once per bus access, during the address cycle. The i960 Kx processor asserts this pin at other times during burst accesses, too, but most systems ignore all other assertions.

· The i960Jx device extends the use of the READY# pin to control the number of recovery (Tr) states between a current bus transaction and the next bus transaction. If system ready logic is configured as Normally-Not-Ready, this new RDYRCV# pin will automatically function as before, i.e., there will be exactly one recovery state.

· WIDTH1:0 pins denote the programmed bus width corresponding to each bus access.

· D/C# indicates data and code accesses, respectively.

· The Burst Last (BLAST#) pin, an important addition, signals the end of a bus access. This pin functions like BLAST# on the i960 Sx and i960 Cx microprocessors.

· CACHE

· BADAC#

The HOLD/HOLDA protocol is enhanced so that the i960Jx processor cannot pass directly from a Td bus state to the Th (HOLD) bus state without passing through the Tr state(s). This change is necessary to support the RDYRCV# pin descr ibed previously. Another difference is that 80960Jx processors will respond to HOLD requests during reset (80960Kx processors cannot). The timing relationship of the HOLD and HOLDA pins will be unchanged.

The 80960Kx device has an open-drain LOCK# output pin and it tests the state of the pin prior to asserting it. The 80960Jx processors have a one-way LOCK# output pin, implemented in three-state logic.

Interrupt Control Inputs

The 80960Jx processor's interrupt control unit will be identical to that of the i960 CA/CF processors. It will have eight general purpose XINT# interrupt pins and one NMI# pin. Note that these are active-low inputs, but, unlike the i960 CA/CF situation, the pins are sampled on the rising clock edge. For future compatibility, avoid u sing the 80960KA/KB processor's Interrupt/Interrupt Acknowledge protocol, as this model is not supported in the i960Jx microprocessor family.

The 80960Jx processors do not support Inter-Agent Communication (IAC messaging), so there is no IAC# input pin.

Other Hardware Compatibility Notes

The active sense of the reset signal changed from high to low.

The LOCK# pin is tested upon RESET# deassertion. If it is low, the processor will enter the ONCE three-state test mode. The 80960Kx processor does not support ONCE mode.

All versions of the new processor will be clocked at the bus frequency, even if the core clock is doubled (80960JD). The i960 Kx processor is clocked at 2X the bus frequency.

Software Considerations

IBR-Initialization Boot Record

The location of the Initialization Boot Record is different on the 80960Jx and the 80960Kx. The IBR on the 80960Kx is located at 0x00000000, while the IBR for the 80960Jx is at 0xFEFFFF30. On the 80960Jx, the area where the 80960Kx IBR is located is in internal data RAM. However on the 80960Kx the area where the 80960Jx boot code is located is reserved.

The formats of the IBRs for these processors are completely different. 80960Jx initialization is much more closely related to the CX processor.

Device ID

A number characte rizing both the microprocessor type and stepping is placed in register g0 upon reset for the 80960Jx. In addition, this device ID is also placed in a memory-mapped register on the 80960Jx and can be accessed directly. The 80960Kx does not have a device ID .

Initialization Code

The initialization code used on the 80960Jx is almost completely compatible with the Cx, and quite different from the 80960Kx. Some of the differences and similarities include the following:

· The PRCB of the 80960Jx does not need to be in RAM like on the 80960Kx, thus no moving of the PRCB and reinitialization is required. The PRCB is not looked at after reset on the 80960Jx. (The initialization is approximately 600 cycles faster without the r einitialization.)

· If the IMI is changed on the 80960Kx, a reinitialization is required afterward. To change the IMI on the 80960Jx simply write to the corresponding MMR (memory mapped register).

· The 80960Jx must reinitialize after moving the interrupt table.

· Stacks and heaps must be in RAM on both the 80960Kx and the 80960Jx.

· The control table does not need to be in RAM on the 80960Jx.

Sample initialization code is available for both the 80960Jx and the 80960Kx in their respective manuals.

Register Values after Reset/Reinitialization

Not all registers on the 80960Jx will contain the same initial values as their counterparts on the 80960Kx. The user should take care to initialize all registers on each part before using them.

Procedure Calls

Procedure calls and related table structures are compatible with the following stipulations:

· The FP and SP on the 80960Kx are always 64-byte aligned. The FP and the SP on the 80960Jx are always 16-byte aligned, eliminating unnecessary padding in the stack. Thus the processor always ignores the lower 4 bits of the FP on the 80960 Jx as opposed to the lower 6 bits on the 80960Kx.

· The 80960Jx does not allow writing to the RIP. An OPERATION.INVALID_OPERAND fault occurs if this is attempted. To update the RIP, execute a flushreg and change the RIP out in memory. The new RIP will then be read in from memory.

· Reserved Return Status Field patterns will result in an OPERATION.UNIMPLEMENTED fault on the 80960Jx.

· The resume bit in the Process Controls register is not implemented on the 80960Jx. This is due to the fact that the 80960Jx has no instruction suspension and resumption mechanism, and does not use resumption records. (Resumption records are used on the 80 960Kx for long floating point instructions.)

· The internal state bits in the Process Controls register are unimplemented on the 80960Jx. The user should not write to these bits on either the 80960Kx or the 80960Jx.

· The 80960Jx does not have a stopped state.

· Register bypassing is implemented on the 80960Jx, and is not on the 80960Kx. The following is an example of this:

mov r6, fp The FP is written out on this step.

addo fp, 0, 55 This instruction does not read in the FP, but uses its value from the previous instruction. The actual FP could differ from the FP used in the addo instruction due to the fact that the processor ignores the lower 4 bits of the actual FP.

The 80960Jx uses the interrupt controller from the CX which is quite different from the 80960Kx. For complete details refer to the users manual.

Memory Control

While the 80960Kx has no built-in memory control, the 80960Jx has 8 programmable memory regions. It contains 8 PMCON registers for programming bus width for the physical memory regions. It also uses 2 types of logical templates each comprised of 2 logical memory control registers (LMMRs and LMADRs) to control data cache enabling for its specific region. The 80960Jx has a default logical memory configuration register (DLMCON) for accesses that do not fall inside one of the two logical memory templates. DLMCON also controls byte ordering for the entire memory map.

IACs

IACs are not implemented on the 80960Jx. The following is a list of all of the 80960Kx IACs and a description of how their functions can be accomplished on the 80960Jx:

· Continue Init IAC is not needed on the 80960Jx.

· The Freeze IAC can be accomplished on the 80960Jx by putting the processor into HALT mode.

· Software Interrupts are done with sysctl on the 80960Jx.

· The Purge Instruction Cache IAC function can be done on the 80960Jx using a sysctl or the new icctl instruction.

· The Reinitialize Processor IAC function can also be done on the 80960Jx using a sysctl.

· The Set Breakpoint IAC function is entirely different on the 80960Jx. It is accomplished by obtaining rights to the breakpoint registers using sysctl. Then the registers can be written to directly as MMR s.

· The Store System Base IAC function is not needed on the 80960Jx because there is no System Address Table on the 80960Jx and the PRCB address is located in an MMR.

· The Test Pending Interrupts IAC function can be performed on the 80960Jx by posting a software interrupt with an invalid vector number in the range of 0-7 . This causes pending interrupts to be rescanned.

Faults

The software handling of faults including related table structures and procedures is compatible, with the following exceptions and additions:

· There are no floating point faults on the 80960Jx.

· The 80960Jx will never generate CONSTRAINT.PRIVILEGED faults, but will generate TYPE.MISMATCH faults instead.

· The Trace Controls Breakpoint/Mark Mode only controls the mark instruction on the 80960Jx, on the 80960Kx it also controls breakpoints. The Breakpoint/Mark Event Flag signals the event of a mark, fmark, or breakpoint fault on both processors.

· The 80960Jx has Parallel faults, Override faults, and system errors and the 80960Kx does not.

· The 80960Jx does not have a trace fault table.

· The system-call trace fault entries on the 80960Kx require the second word of the entry to be 0x27F. This 0x27F is also specified on the 80960Jx, however it is ignored.

· There is a new fault, OPERATION.UNALIGNED, on the 80960Jx which is not on the 80960Kx.

· There is a new fault resumption record added to the fault record to be used for Parallel and Override faults on the 80960Jx.

Tracing and Debugging

There are no major tracing and debugging differences between the 80960Jx and the 80960Kx. Several minor difference include:

· The 80960Kx and the 80960Jx have 2 instruction address breakpoints. In addition, the 80960Jx has 2 data address breakpoints.

· The breakpoint registers on the 80960Jx are located in MMRs. Application code on the 80960Jx must first request and acquire modification rights to the hardware breakpoint resources (BPCON s) before any attempt is made to modify them. This procedure is not required on the 80960Kx.

· Bits 27:24 of the trace controls describe Hardware Breakpoint Event Flags on the 80960Jx. These bits are reserved on the 80960Kx.

· Bits 23:17 of the trace controls describe trace event occurrences on the 80960Kx. These bits are reserved on the 80960Jx.

Instructions

The 80960Kx and the 80960Jx contain the same basic instruction set with the following exceptions:

· New instructions on the 80960Jx (designated in the i960Ò Jx Microprocessor Users Manual) are not compatible with the 80960Kx.

· The 80960Jx has more supervisor instructions than the 80960Kx including: dcctl, icctl, intctl, indis, halt, sysctl. The use of these instructions while not in supervisor mode will result in a TYPE.MISMATCH fault.

· daddc and other decimal and floating point instructions are not supported on the 80960Jx.

· synmov instructions were used for IACs and are not present on the 80960Jx.

Floating Point

The 80960KB contained a floating point unit, while the 80960Jx does not, so obviously there are no floating point registers on the 80960Jx. In addition, the floating point bits in the Arithmetic Controls will have no effect on the 80960Jx processor. In other words, no other function has been assigned to them.

Data RAM, Local Registers, and MMRs

The 80960Jx has 1K of on-chip data RAM located at 0x00000000. The 80960Kx does not contain any on-chip data RAM.

Another memory map conflict includes the reserved memory space on the 80960Kx (0xff000000 - 0xffffffff) which is where the Memory Mapped Registers on the 80960Jx are located.

The 80960Kx has 4 register sets while the 80960Jx ha s 8 register sets. The 80960Jx can also reserve between 0 and 7 sets for high priority interrupts, and uses the Register Cache Configuration Word in the PRCB to program local register availability.

Caches

The instruction cache on the 80960JA is 2K while the 80960JF and 80960JD are 4K. The instruction cache on the 80960Kx is only 512 bytes.

The data cache on the 80960JA is 1K. While the 80960JF and 80960JD have 2K of data cache. All are direct mapped. The 80960Kx does not have a data cache.

Other Compatibility Notes

The 80960Jx has no multiprocessing capability like the 80960Kx does.

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