Creating Cacheable Contiguous Memory Partitions on the 80960JX Using Logical Memory Control Registers (LMCONs)

August 25, 1995
Revision 1.2

Intel's i960Jx processors have the capability to program two specific contiguous regions in their memory space as being cacheable, with the rest of the memory space being non-cacheable or vice versa. These regions are programmmed using the Logical Memory Attributes Registers: LMADR0-1 and LMMR0-1. Due to the nature of the programming mechanism, it is not always possible to include all of the contiguous memory between arbitrary starting and ending addresses.

This document describes how to determine what should be programmed into the Logical Memory Attributes Registers given the desired starting and ending addresses for the memory region. It is intended to supplement the Memory Configuration chapter found in the user's manual. Users may find this paper helpful when the address boundaries requied by a system are not easily programmable in the Logical Memory Attributes Registers. For detailed information on 80960Jx processors please refer to the following:
Electrical specifications for the 80960Jx product are found in the following documents:

• 80960 JA/JF Embedded 32-Bit Processor Data Sheet, Order #272504
• 80L960 JA/JF 3.3V Embedded 32-Bit Processor Data Sheet, Order #272744
• 80960 JD Embedded 32-Bit Processor Data Sheet, Order #272596

• i960Jx Microprocessor User's Manual, Order #272483

The following procedure can be used to determine the largest amount of contiguous memory possible between any arbitrary starting and ending addresses using one LMCON (Logical Memory Control) register pair. This procedure assumes that it is permissible not to include some pieces of memory that can be mapped as cacheable. It does ensure, however, never to map a non-cacheble area as cacheable.

It should be noted that this method does not necessarily need to be used if the starting address and size of the cacheable memory regions in a system conforms to the following rules:

Let the number of bytes between the starting and ending addresses be defined as "D". Then only when "D" is an integer power of 2, and the starting address is an integer multiple of "D", can all of the addresses be mapped with one pair of LMCON registers.

Procedure:

1. Let (addr1, addr2) be the range of addresses that need to be mapped using the LMCON registers. addr1 is the starting address inclusive and addr2 is the ending address inclusive.

   Let D = 2^{int( log2( (addr2+1) - addr1) )} ;

   Let d = D/2;

   D represents the largest area of contiguous area that can be mapped between addr1 and addr2. d represents the smallest area of contiguous area that can be mapped between addr1 and addr2

2. Use the following equation to determine the first aligned boundary of D and d in (addr1, addr2).
   
   

   ceiling(n) = n;	# If n is an integer
   = int(n+1);			# If n is not an integer

   
   Dstart = D * ceiling(addr1/D);
   dStart = d * ceiling(addr1/d);

   if(( DStart+D-1) <= addr2)

   {	Start = Dstart;
   	Size = D;
   }

   else

   {	Start = dStart;
   	Size = d;
   }

   The suggested area to be mapped for arbitrary addresses (addr1, addr2) is (Start, Start + Size - 1).

3. To program the LMCON registers for (Start, Start + Size - 1) use the following equations:
   Cacheable = 2 for yes and 0 for no.
   Enable_Template = 1 for yes and 0 for no.

   LMADR = Start + Cacheable;
   LMMR = not( Size - 1) + Enable Template;
   
   

   Example #1

   Map the region (0, 0x00DFFFFF) as cacheable.

   1. D = 2 ^{int( log2( (0x00DFFFFF +1) - 0) )};
   D = 0x00800000;
   d = 0x00400000;

   2. Dstart = 0x00800000 * ceiling(0/0x00800000);
      
   Dstart = 0;
   dStart = 0x00400000 * ceiling(0/0x00400000);
   dStart = 0;

   (0 + 0x00800000 -1) is <= 0x00DFFFFF therefore:
   

   Start = 0;
   Size = 0x00800000;

   3. The suggested area to be mapped as cacheable is (0, 0x007FFFFF). Program the LMCON registers as follows:
   Cacheable = 2;
   Enable_Template = 1;

   LMADR = 0x2;

   LMMR = not(0x007FFFFF) +1;
   = 0xFF800001;

   Example #2

   Map the region (0x00F00000, 0x0FFFFFFF) as cacheable.

   1. D = ^{int( log2( (0x0FFFFFFF +1) - 0x00F00000) )};
      D = 0x08000000;
      d = 0x04000000;

   2. Dstart = 0x08000000 * ceiling(0x00F00000/0x08000000);
      Dstart = 0x08000000;
      dStart = 0x04000000 * ceiling(0x00F00000/0x04000000);
      dStart = 0x04000000;

      (0x08000000 + 0x08000000-1) is <= 0x0FFFFFFF therefore:
      

      Start = 0x08000000;
      Size = 0x08000000;

   The suggested area to be mapped as cacheable is (0x08000000, 0x0FFFFFFF). Program the LMCON registers as follows:
   
   Cacheable = 2;
   Enable_Template = 1;

   LMADR = 0x08000002;

   LMMR = not(0x07FFFFFF) +1;
   = 0xF8000001;

   Example #3

   Map the region (0x00E5C000, 0x00F93FFF) as cacheable.

   1. D = 2^{int( log2( (0x00F93FFF +1) - 0x00E5C000) )} ;
      D = 0x00100000;
      d = 0x00080000;

   2. Dstart = 0x00100000 * ceiling(0x00E5C000/0x00100000);
      Dstart = 0x00F00000;
      dStart = 0x00080000 * ceiling(0x00E5C000/0x00080000);
      dStart = 0x00E80000;

      (0x00F00000 + 0x00100000-1) is not <= 0x00F93FFF therefore:
      

      Start = 0x00E80000;
      Size = 0x00800000;

   The suggested area to be mapped as cacheable is (0x00E80000, 0x00EFFFFF). Program the LMCON registers as follows:
   
   Cacheable = 2;
   Enable_Template = 1;

   LMADR = 0x00E80002;

   LMMR = not(0x0007FFFF) +1;
   = 0xFFF80001;

   
   
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