i960® CA/CF Microprocessors's Self Test

Introduction

The i960^® CA/CF processors can execute two self tests on power-up or reset (an internal function test and an external bus confidencetest). The tests provide approximately 88% toggle coverage in approximately 65,000 cycles on the i960^® CA and approximately 280,000 cycles on the i960^® CF.

After the self tests have completed successfully, system diagnostics may be executed with the knowledge that the processor is working properly.

Self Test Flow

Figure 1 shows how the self test algorithms are placed in the processors initialization sequence.

Figure 2 indicates the relationship between the self tests and the RESET#, FAIL#, and STEST signals.

Initialization begins on the rising edge of RESET#. At this time, if STEST is asserted, the internal test will be executed. If STEST is deasserted, the internal test will be disabled.

The FAIL# pin is asserted during the execution of both the internal and bus confidence tests, but is toggled for five cycles after the internal test to indicate that the test passed. If the internal test is bypassed, the FAIL# pin still toggles at the point where the internal test would occur.

If either of the tests fail, the FAIL# pin will remain asserted. Otherwise, the FAIL# pin is deasserted on completion of the bus confidence test.

When studying the following figures, notice the many test points in which the processor can stop execution on failure.

Figure 1. Self Test Algorithms During Initialization

Figure 2. i960^® CX Self Test Timing

Internal Self Test
The internal self test on the i960^® CA/CF processor tests the basic functionality of the internal units. The internal units are divided into memory arrays and functional units. Memory arrays are tested by writing patterns to the array and checking if the value read back is the same. Functional units, on the other hand, are tested by exercising the function that the unit performs and verifying that it is executed correctly.

Figure 3 shows the flow of the internal self test algorithm. The test is divided into three major sections:

Data Cache Test (i960^® CF only)
Functional Unit Test
Instruction Cache Test

Figure 3. Internal Self Test Algorithm
Data Cache Test (i960^®CF only)

The algorithm for testing the data cache is shown in Figure 4. The data patterns 0x55555555 and 0xAAAAAAAA were chosen because they provide maximum toggle coverage.

The data algorithm loads and stores data patterns in an alternate pattern. This sequence of loads and stores to the cache is repeated until the entire cache (1K-bytes) is tested. Each time data is loaded from the cache, it is added to a checksum. At the end of the test, this checksum value is compared with the expected checksum value to determine if the test has passed or failed.

Functional Unit Test

This section of the internal self test uses different methods to test the various units. The heart of the algorithm is in testing:

Stack Ram (sr) tested like memory arrays by

The algorithm also tests some units by actually exercising each unit's functions:

Execution Unit (eu) arithmetic operations

Multiply and Divide Unit (mdu) multiply and divide operations

The other units are tested in a more implicit way. The execution of the test instructions serves as a test of the core units:

Address generation unit (agu) instruction decoder (id)

parallel instruction scheduler (pis) instruction fetch unit (ifu)

For every test of a functional unit, the checksum is updated. At the end of all the tests, the computed checksum value is compared with the expected checksum value to verify the success of the test. The algorithm is shown in Figure 5.

Figure 4. Data Cache Test Algorithm (80960 CF Only)

Figure 5. Functional Unit Test Algorithm
Instruction Cache Test

The instruction cache is tested in the same way the data cache is tested in that alternating patterns of 5's and A's are written to the cache and read back to verify the value that was written.

his test also toggles the tag arrays (unlike the data cache) by switching the address patterns between 5's and A's.

e algorithm, shown in Figure 6, loops through the cache three times alternating the pattern. After the cache is filled up with a pattern, it is read back and added to a checksum. After the three loops, the calculated checksum is verified against the expected checksum.

External Bus Confidence Test

The external bus confidence test checks external bus functionality. This test is performed by reading eight words from the Initialization Boot Record (IBR) and performing a checksum on the words and the constant 0xFFFFFFFF. If the processor calculates a sum of zero, the test passes.

The external bus confidence test can detect catastrophic bus failures such as shorted address, data or control lines in the external system.

Figure 6. Instruction Cache Test Algorithm