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October 3rd, 1992
Revision 1
This document covers the alignment restrictions for DMA transfers on both the 80960CA and 80960CF. The current steppings do not support the entire alignment descriptions covered in the i960(R) CA Microprocessor User's Manual. We are adding some functionality to the next steppings to fully support the descriptions in the User's Manual.
The existing DMA functionality limits the alignment of the synchronizing device to the transfer width. The non-synchronized half of the transfer can be aligned on a byte boundary. For example, for a 32-32 source synchronized transfer, the source must be aligned to a 32-bit boundary, while the destination may be aligned to a byte boundary. For a 32-32 destination synchronized transfer, the source can be aligned to a byte boundary but the destination must be aligned to a 32-bit boundary.
The byte count must also be aligned to the transfer width boundary, or evenly divisible by the transfer width.
There is only one known errata with these modes, listed in the current errata lists as A26. It is attached to the end of this document for convenience.
These steppings will support any alignment for source, destination address, and byte count in the incrementing address modes. This is how the current User's manual reads.
Synchronized transfer width is defined to be the size of the data type correlating to the synchronized mode.
The synchronized transfer width is either a byte, short-word, word, or quad-word data type. For a 32- to 16-bit transfer, the transfer width is 32-bits for source synchronization, and is 16-bits if using destination synchronization.
The following discussions cover the case of incrementing source and destination address.
The source address must be aligned on the transfer width boundary. For example, if the transfer mode is 32 to 8-bits, the source address must be word aligned.
The byte count must be aligned on the same boundary as the source address, or evenly divisible by the transfer width. for example, in 32-8 bit transfer mode, the byte count must be evenly divisible by 4.
The destination address can be aligned on a byte boundary.
The number of DREQ#s required to complete the transfer is equal to the byte count divided by the transfer width. When the destination is not aligned on the transfer width boundary, the DMA should align the destination to the transfer width boundary for the first transfer, and then transfer any remaining bytes when terminal count is reached. The destination address must be able to tolerate stores that range from 1 byte to the (2*transfer width - 1) bytes. For example, consider a 32-32 transfer from an aligned source address of 200 and a destination unaligned by 1 at a address of 301, and a byte count of 16.
| DREQ# | SOURCE | DESTINATION |
| 1. | word load @ 200 | byte store @ 301 |
| byte store @ 302 | ||
| byte store @ 303 | ||
| 2. | word load @ 204 | word store @ 304 |
| 3. | word load @ 208 | word store @ 308 |
| 4. | word load @ 20C | word store @ 30C |
| byte store @ 300 |
In this example, if the destination address had been at 303, the DMA would have transferred 1 byte for the first DREQ#, and 7 bytes for the last DREQ#.
See errata description for certain cases.
| Transfer Types | Boundary Alignment Requirements | ||||
| (Source-to-Destination) | Byte Count | Source Address or Fly-by Address | Destination Address | ||
| Fixed | Incr. | Fixed | Incr. | ||
| Byte-to-Byte (8/8 bit) Multi-cycle Fly-by | Byte Byte | Byte Byte | Byte Byte | Byte N/A | Byte N/A |
| Byte-to-Short (8/16 bit) Multi-cycle | Byte | Byte | Byte | Short | Byte |
| Byte-to-Word (8/32 bit) Multi-cycle | Byte | Byte | Byte | Word | Byte |
| Short-to-Byte (16/8 bit) Multi-cycle | Short | Short | Short | Byte | Byte |
| Short-to-Short (16/16 bit) Multi-cycle Fly-by | Short Short | Short Short | Short Short | Short N/A | Byte N/A |
| Short-to-Word (16/32 bit) Multi-cycle | Short | Short | Short | Word | Byte |
| Word-to-Byte (32/8 bit) Multi-cycle | Word | Word | Word | Byte | Byte |
| Word-to-Short (32/16 bit) Multi-cycle | Word | Word | Word | Short | Byte |
| Word-to-Word (32/32 bit) Multi-cycle Fly-by | Word Word | Word Word | Word Word | Word N/A | Byte N/A |
| Quad-to-Quad (128/128 bit) Multi-cycle Fly-by | Quad Quad | Quad Quad | Quad Quad | Quad N/A | Quad N/A |
The source address can be byte aligned.
The destination address must be aligned on the transfer boundary. For example, in 8-32 bit transfer mode, the destination address must be word aligned.
The byte count must be aligned on the same boundary as the destination address, or evenly divisible by the transfer width. For Example, in 8-32 bit transfer mode, the byte count must be evenly divisible by 4.
The number of DREQ#s required to complete the transfer is equal to the byte count / 4. When the source is not aligned on the transfer width boundary, the DMA aligns the source address to the transfer width boundary and then cleans up the transfer at the end. The source address must be able to tolerate providing loads from 1 to (2*transfer width - 1) bytes. For example, consider a 32-32 transfer from an aligned destination of 200 and a source address unaligned by 1 at address 301, and a byte count of 16.
| DREQ# | SOURCE | DESTINATION |
| 1. | word load @ 300 | |
| word load @ 304 | word store @ 200 | |
| 2. | word load @ 308 | word store @ 204 |
| 3. | word load @ 30C | word store @ 208 |
| 4. | word load @ 310 | word store @ 20C |
| Transfer Types | Boundary Alignment Requirements | ||||
| (Source-to-Destination) | Byte Count | Source Address or Fly-by Address | Destination Address | ||
| Fixed | Incr. | Fixed | Incr. | ||
| Byte-to-Byte (8/8 bit) Multi-cycle Fly-by | Byte Byte | Byte Byte | Byte Byte | Byte N/A | Byte N/A |
| Byte-to-Short (8/16 bit) Multi-cycle | Short | Byte | Byte | Short | Short |
| Byte-to-Word (8/32 bit) Multi-cycle | Word | Byte | Byte | Word | Word |
| Short-to-Byte (16/8 bit) Multi-cycle | byte | Short | Byte | Byte | Byte |
| Short-to-Short (16/16 bit) Multi-cycle Fly-by | Short Short | Short Short | Byte Short | Short N/A | Short N/A |
| Short-to-Word (16/32 bit) Multi-cycle | Word | Short | Byte | Word | Word |
| Word-to-Byte (32/8 bit) Multi-cycle | Byte | Word | Byte | Byte | Byte |
| Word-to-Short (32/16 bit) Multi-cycle | Short | Word | Byte | Short | Short |
| Word-to-Word (32/32 bit) Multi-cycle Fly-by | Word Word | Word Word | Byte Word | Word N/A | Word N/A |
| Quad-to-Quad (128/128 bit) Multi-cycle Fly-by | Quad Quad | Quad Quad | Quad Quad | Quad N/A | Quad N/A |
These steppings will retain the functionality of the existing steppings. In addition, these steppings will allow both the source address, destination address, and byte count to exist on byte boundaries for the incrementing address modes. Both the fly-by and fixed address modes would still need to align the byte count and the addresses to the appropriate boundary. The reason for this is obvious.
These fully unaligned transfer modes would only be useful for memory-to-memory transfers. If both the source and destination address is unaligned, the DMA will generate byte loads and stores until the destination is aligned. The same location may be read more than once while the transfer is being aligned. Also, the synchronizing device may be be required to supply fewer or more bytes per transfer. For example, in 32-32 bit destination synchronized demand mode, the destination could be written with 1 to 7 bytes per DREQ#. The number of DREQ#s required to complete the transfer is very difficult to calculate, given the large number of permutations. It may be greater than the byte count divided by the transfer width.
Each DREQ# will generate a single DACK#. This will make it much easier for external hardware to assert DREQ#, based on the DACK# output.
For example, consider a 32-32 bit source synchronized transfer with source at 0201, destination at 0303, and a byte count of 12.
| DREQ# | SOURCE | DESTINATION |
| 1. | byte load @ 0201 | byte store @ 0303 |
| 2. | word load @ 0200 | |
| 3. | word load @ 0204 | word store 304 |
| 4. | word load @ 0208 | word store 308 |
| 5. | word load @ 020C | byte store 30C |
| byte store 30D | ||
| byte store 30E |
| Transfer Types | Boundary Alignment Requirements | ||||
| (Source-to-Destination) | Byte Count | Source Address or Fly-by Address | Destination Address | ||
| Fixed | Incr. | Fixed | Incr. | ||
| Byte-to-Byte (8/8 bit) Multi-cycle Fly-by | Byte Byte | Byte Byte | Byte Byte | Byte N/A | Byte N/A |
| Byte-to-Short (8/16 bit) Multi-cycle | Byte | Byte | Byte | Short | Byte |
| Byte-to-Word (8/32 bit) Multi-cycle | Byte | Byte | Byte | Word | Byte |
| Short-to-Byte (16/8 bit) Multi-cycle | Short | Short | Byte | Byte | Byte |
| Short-to-Short (16/16 bit) Multi-cycle Fly-by | Short Short | Short Short | Byte Short | Short N/A | Byte N/A |
| Short-to-Word (16/32 bit) Multi-cycle | Short | Short | Byte | Word | Byte |
| Word-to-Byte (32/8 bit) Multi-cycle | Word | Word | Byte | Byte | Byte |
| Word-to-Short (32/16 bit) Multi-cycle | Word | Word | Byte | Short | Byte |
| Word-to-Word (32/32 bit) Multi-cycle Fly-by | Word Word | Word Word | Byte Word | Word N/A | Byte N/A |
| Quad-to-Quad (128/128 bit) Multi-cycle Fly-by | Quad Quad | Quad Quad | Quad Quad | Quad N/A | Quad N/A |
The DMA controller is optimized to perform unaligned 32-32 bit transfers. However, when in source-synchronized demand mode, the DMA controller requires an extra DREQ# to complete the transfer when the destination address is unaligned.
For example, assume an aligned source address and a destination address which is unaligned by one byte (has an address of xxxxxxxx1) and a byte count of 16. The DMA controller should transfer 3 bytes for the first DREQ#, 4 bytes the two middle DREQ#s, and 5 bytes for the last DREQ#. However, the current stepping only transfers 4 bytes for the 4th DREQ# and requires a 5th DREQ# to transfer the last byte. The workaround is to always ensure that your destination address is aligned on a 4 byte boundary, or have your hardware generate an extra DREQ#. This errata will be fixed on the C-stepping.
All other source synchronized transfer modes with an unaligned destination address will work correctly. (ie 16-16, 8-8, etc)
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