Easy upgrade from the 80960KX to the 80960JX

22 December 1993
Revision 1.3

Bus Organization
Control Signals
Bus Arbitration
Interrupt Control Inputs

Intel is currently developing a new implementation of the i960(R) architecture designated internally as the JX microprocessor. Intel intends the JX processor to be an easy upgrade choice from the existing 80960KA/KB microprocessor and is paying special attention to bus and control signal compatibility issues in the design process.

If you are presently designing a system or companion chip based on the 80960KA/KB processor and you anticipate upgrading to the JX processor in the future, you can plan for that transition by following suggestions in this technical note.

Note: This document contains information on products in the design phase of development. This information is subject to change without notice.

BUS ORGANIZATION

Like the 80960KA/KB processor, the JX device will have a 32-bit, multiplexed address/data bus capable of high bandwidth burst transfers. Although the JX will occupy the same 132-lead PQFP and PGA packages and have similar control signals, it will not be pin-compatible to the existing 80960KA/KB device.

Enhancements to the bus include demultiplexed, incrementing address signals A3:2 and programmable bus width. For 16-bit buses, the processor will drive address signal A1 on the BE1# pin. For 8-bit buses, the processor will also drive address signal A0 on the BE0# pin. This addressing convention corresponds to the 80960CX processors.

CONTROL SIGNALS

The new microprocessor will use three-state output buffers instead of open-drain buffers for all control signal outputs. This change could affect a few existing 80960KX designs that have multiple processors sharing a memory subsystem.

The following list identifies control signals that will be directly compatible to their 80960KA/KB counterparts:

During the address cycle, pins AD1:0 will denote SIZE bits to indicate the length of a burst. The functionality of these pins will be extended to 8- and 16- bit bus widths, where the maximum number of transfers is also four.
ALE# will work identically. For new design work, the complementary ALE signal will be available also.
Byte enables BE3:0# on the 80960KX processor are valid at least one clock before the corresponding data state of a burst. Byte enables may change states during a burst access to qualify unaligned data transfers. In other words, the byte enables are pipelined and toggling and external system logic must latch the signals. Microcode in the JX processor will break up requests for unaligned data into smaller bus accesses which will always be individually aligned. The JX processor will drive appropriate BE3:0# pins active during Ta and inactive during Tr. The pins do not toggle within the burst, so there is no need to latch them. Existing system logic designed for pipelined, toggling byte enables will automatically handle the new BE3:0# signals as a trivial case.
W/R#, DT/R# and DEN# pins function identically.

The following list identifies control signals that may require minor changes to an existing design based on the 80960KA/KB processor:

The new processor will assert ADS# only once per bus access, during the address cycle. The i960KX processor asserts this pin at other times during burst accesses, too, but most systems ignore all other assertions.
The JX device will extend the use of the READY# pin to control the number of recovery (Tr) states between a current bus transaction and the next bus transaction. If system ready logic is configured as Normally-Not-Ready, this new RDYRCV# pin will automatically function as before, i.e., there will be exactly one recovery state.

The following list identifies new control signals that will be provided for the JX processors but are absent on the i960KX processors:

WIDTH1:0 pins will denote the programmed bus width corresponding to each bus access.
D/C# will indicate data and code accesses, respectively.
The Burst Last (BLAST#) pin, an important addition, will signal the end of a bus access. This pin will function like BLAST# on the i960SX and i960CX microprocessors.

The following list enumerates 80960KX control signals that are not supported by the new processor:

CACHE
BADAC#

BUS ARBITRATION

The HOLD/HOLDA protocol will be enhanced so that the JX processor cannot pass directly from a Td bus state to the Th (HOLD) bus state without passing through the Tr state(s). This change is necessary to support the RDYRCV# pin described previously. The timing relationship of the HOLD and HOLDA pins will be unchanged.

The 80960KX device has an open-drain LOCK# output pin and it tests the state of the pin prior to asserting it. The JX processor will have a one-way LOCK# output pin, implemented in three-state logic.

INTERRUPT CONTROL INPUTS

The JX processor's interrupt control unit will be identical to that of the i960CA/CF processors. It will have eight general purpose XINT# interrupt pins and one NMI# pin. Note that these are active-low inputs, but, unlike the i960CA/CF situation, the pins will be sampled on the rising clock edge. For future compatibility, avoid using the 80960KA/KB processor's Interrupt/Interrupt Acknowledge protocol, as this model will not be supported in the JX device.

The JX processor will not support Inter-Agent Communication (IAC messaging), so there is no IAC# input pin.

OTHER COMPATIBILITY NOTES

The active sense of the reset signal will change from high to low.

The LOCK# pin will be tested upon RESET# deassertion. If it is low, the processor will enter the ONCE three-state test mode. The 80960KX processor does not support ONCE mode.

All versions of the JX processor will be clocked at the bus frequency, even if the core clock is doubled. The i960KX processor is clocked at 2X the bus frequency.