ACCELERATED GRAPHICS PORT INTERFACE SPECIFICATION

THESE APPROVED CHANGES TO THE ACCELERATED GRAPHICS PORT INTERFACE SPECIFICATION, REVISION 1.0 ARE PROVIDED “AS IS” WITH NO WARRANTIES WHATSOEVER INCLUDING ANY WARRANTY OF MERCHANTABILITY, FITNESS FOR ANY PARTICULAR PURPOSE, OR ANY WARRANTY OTHERWISE ARISING OUT OF ANY PROPOSAL, SPECIFICATION, OR SAMPLE. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHT IS GRANTED OR INTENDED HEREBY. INTEL DISCLAIMS ALL LIABILITY, INCLUDING LIABILITY FOR INFRINGEMENT OF PROPRIETARY RIGHTS, RELATING TO IMPLEMENTATION OF INFORMATION IN THESE SPECIFICATION CHANGES. INTEL DOES NOT WARRANT OR REPRESENT THAT SUCH IMPLEMENTATION(S) WILL NOT INFRINGE SUCH RIGHTS. INTEL INTENDS TO INCLUDE THESE SPECIFICATION CHANGES AS A PART OF THE FUTURE ACCELERATED GRAPHICS PORT INTERFACE SPECIFICATION REVISION 2.0. A RECIPROCAL, ROYALTY-FREE LICENSE TO THE ELECTRICAL INTERFACES AND BUS PROTOCOLS DESCRIBED IN, AND REQUIRED BY, THE ACCELERATED GRAPHICS PORT INTERFACE SPECIFICATION REVISION 2.0 WILL BE AVAILABLE FROM INTEL WHEN REVISION 2.0 OF THAT SPECIFICATION IS PUBLICLY RELEASED.

Copyright © 1996, Intel Corporation

• ECR#1 (11/15/96)
  • Clarification of "0" and what it means for RQ_DEPTH command and status register
• ECR#2 (11/15/96)
  • Clarification of the buffer V-I equations to match figure 4-17
• ECR#3 (11/15/96)
  • Changing VIL and VIH in table 4-2 to match the value in table 4-1
• ECR#4 (11/15/96)
  • Clarification of the fact that AGP is a standalone specification by removing any reference to the PCI specification
• ECR#5 (11/15/96)
  • Clarification of the statement on settling time (Tset) having no direct detrimental impact on AGP interconnect performance
• ECR#6 (11/15/96)
  • Clarification of the protocol on 1X (request) followed by 2X (write data) with no turnaround cycle
• ECR#7 (11/15/96)
  • Clarification of figure 3-39 to use figure 8-29 in place of 8-28
• ECR#8 (11/15/96)
  • Clarification of figure 8-77 to show GNT# asserted from clock 2-7
• ECR#9 (11/15/96)
  • Clarification of footnote 16 on page 55
• ECR#10 (12/11/96)
  • Clarification of section (4.2.2.3) to remove the 50 Ohm loading.
• ECR#11 (2/10/97)
  • Change to PCI target latency exception
• ECR#12 (2/10/97)
  • Clarification to trace lengths and skew timings
• ECR#13 (2/10/97)
  • Change to remove SMB1 and SMB0 from connector
• ECR#14 (2/10/97)
  • Change to add USB overcurrent pin
• ECR#15 (2/10/97)
  • Clarifications to Fig 5-1, Fig 5-2, Fig 5-4, and Table 5-1
• ECR#16 (2/10/97)
  • Clarification to AGP to PCI memory write support
• ECR#17 (2/10/97)
  • Clarification of Section 6.1.2
• ECR#18 (2/17/97)
  • Change to add PME# -- Power Management Pin
• ECR#19 (2/17/97)
  • Change to avoid arbitration deadloc
• ECR#20 (2/17/97)
  • Change to add monochrome display adapter support
• ECR#21 (2/17/97)
  • Clarification to correct pull-up resistor errors
• ECR#22 (2/17/97)
  • Clarification to IDSEL and an AGP-compliant master
• ECR#23 (2/17/97)
  • Change to power requirements for the power rails and make AGP power supply tolerance +5%
• ECR#24 (2/17/97)
  • Clarification to avoid a potential deadlock on AGP
• ECR#25 (2/17/97)
  • Clarification of Fig. 3-21 text
• ECR#26 (2/17/97)
  • Clarification to requirement of actively driving xRDY#
• ECR#27 (3/3/97)
  • Clarification to the specification for strobe widths
• ECR#28 (3/3/97)
  • Change to the control setup and output valid times
• ECR#29 (4/7/97)
  • Change to ECR#15

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