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Intel Blocked Flash Memory 28F001BX-B/28F001BX-T
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- Supports modular code development and updates
- Simplifies code updates
- Extends battery life
- Improved wait-state performance
- Secures boot code
- High-integration blocked architecture
- Simplified program and erase
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-Automated algorithm via on-chip write-state machine
- Deep-powerdown mode
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-0.05µA Icc typical
-0.08µA Ipp typical
- High-performance read
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-70ns maximum access time
- Hardware data protection feature
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-Erase/write lockout during power transitions
- JEDEC standard packages
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-32-pin PDIP
-32-lead PLCC, TSOP
Intel's 28F001BX-B and 28F001BX-T blocked flash memories combine the cost-effectiveness of Intel standard flash memory with features that simplify write and allow block erase. By combining the functions of several components in one, these devices make flash memory an innovative alternative to EPROM and EEPROM or battery-backed static RAM.
The 28F001BX-B and 28F001BX-T 1-Mbit (128Kx8) blocked flash memories augment the nonvolatility, in-system electrical erasure and reprogrammability of Intel's standard flash memory. Many new and existing designs can take advantage of these devices' integration of blocked architecture, automated electrical reprogramming and standard processor interface. The blocked flash memories offer four separately erasable blocks and integrate a state machine to control erase and program functions. The specialized blocking architecture and automated program-ming of the 28F001BX family provide a full-function, nonvolatile flash memory ideal for a wide range of applications, including PC/BIOS memory, minimal-chip embedded program memory and parametric data storage.
The 28F001BX family combines the safety of a hardware-protected 8 Kbyte boot block with the flexibility of three separately reprogrammable blocks (two 4 Kbyte parameter blocks and one 112 Kbyte code block) into one versatile cost-effective flash memory. As reprogramming one block does not affect code stored in another block, data integrity is ensured.
The 28F001BX-T's block locations provide compatability with microprocessors and microcontrollers that boot from high memory, such as Intel's i486(TM), i386(TM), and 80186 families. The 28F001BX-B memory map is tailored for bottom-boot devices such as Intel's MCS(R) 51, MCS(R) 96, 80960KX and 80960SX microcontrollers and processors.
| FEATURES | BENEFITS |
| High-integration blocked architecture | One 8-KB boot block with lock-out Two 4-KB parameter blocks One 112-KB main block |
| Simplified program and erase | Automated algorithms via on-chip write-state machine |
| Deep-powerdown mode | 0.05u Icc typical 0.08u Ipp typical |
| High-performance read | 70ns maximum access time |
| Hardware data protection | Erase/write lockout during power transitions |
| Flexible packaging | JEDEC pinouts 32-pin PDIP 32-lead PLCC, TSOP |
| Industrial temperature range available | Wide range of applications |
Order Number 296913-004
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