The 87C196JT is a high memory, high performance member of the 87C196Kx/Jx 16-bit microcontroller family. The large 32 Kbyte EPROM program memory and 1.5 bytes on-chip RAM provides the large memory storage demanded by today's software algorithms.

The 87C196JT is a high performance member of the industry standard, Intel MCS(R) 96 microcontroller family. The 87C196JT provides the high memory integration of the MCS 96 microcontroller family, having 32 Kbyte of on-chip EPROM memory, 1 Kbyte of register RAM, and 512 bytes of code RAM. The 87C196JT is a pin-to-pin compatible memory upgrade from the 87C196JR. The register architecture of the MCS 96 microcontroller family eliminates accumulator bottleneck and enables fast context switching which increases execution time of C programs. The 512 bytes of code RAM can be used to modify critical loops and execute code internally. The 87C196JT has bit, byte, word, and some 32- bit instructions and is available in 16 MHz and 20 MHz versions. The high performance microcontroller is capable of 16 x 16-bit multiply in 1.75µ S, and 32/16-bit divide in 3µS when operating at 16 Mhz.

The 87C196JT has a complete enhanced set of integrated peripherals and is available in a low-cost 52 lead PLCC package. It offers a six channel A/D with 8- or 10-bits of resolution. The 87C196JT has a configurable 8- or 16-bit bus. The 87C196JT has 12 modularized high speed I/O units called the Event Processor Array (EPA). Six units are pinned out for I/O event compare and capture and six are available for internal event timing.

The 87C196JT offers a Peripheral Transaction Server (PTS), which is an alternative way to service an interrupt, reducing latency and overhead, similar to a DMA. The PTS is capable of handling single and block transfers, A/D conversions, and EPA events without executing an interrupt service routine.The 87C196JT has 41 I/O lines, 2 serial ports, a watchdog timer, two 16-bit timers, and oscillator fail detect circuitry. Intel's CHMOS process technology combines low power consumption and high performance. Idle and powerdown modes are available to further reduce power consumption.

Features

Benefits

Industry standard MCS 96 architecture 32 Kbyte on-chip EPROM 1 Kbyte on-chip register RAM 512 bytes on-chip code RAM 1.5µS 16 x 16 multiply 3µS 32/16 divide 16 MHz operation Event Processor Array Peripheral Transaction Server 8- or 10-bit A/D converter with sample and hold Configurable 8- to 16-bit external bus Full duplex serial port Two 16-bit timers

Large program memory array No accumulator bottleneck Fast context switching Updatable run time code Fast, precise control Compact calculation loops High resolution timing of multiple events Fast handling of external events without interrupt service routine overhead Reduced board space, accurate feedback Communication with standard devices Connects with peripherals and other processors Versatile event tracking Low cost 52 Lead PLCC package Oscillator fail detect