• Overview
• Die Level Burn-In/Test (DLBI/T)
• SmartSort

• User's Guide Table of Contents

Note 2: *= Statistical Bin Limits Implemented

Wafer Fab
Wafers for SmartDie products are fabricated on standard Intel fabrication processes. They are identical to wafers that are used for packaged products.

Sort
Standard Intel wafer level electrical tests. Sort is done at room temperature.

Wafer Saw
The wafers are sawed with a process that contains an extended wash cycle. The wash nozzles are extended to increase the water force at the surface of the wafer to increase the effectiveness of removing silicon particles generated by the saw process.

Die Carrier Load
Die are loaded into the die carriers which acts as a temporary package during test and burn-in. The die carrier has been designed to withstand the temperature extremes of test and burn-in. This is an automated process that accurately aligns the contacts in the die carrier with the bond pads on the die.

Burn-In
Die carriers are loaded into burn-in boards. Burn-in duration for SmartDie DLBI/T products is the same as the equivalent packaged products.

Electrical Test
The post burn-in electrical test is done at hot and cold temperatures.

Die Carrier Unload
Die are unloaded from the carriers and accurately placed in carbon conductive Gel-Paks. This is also an automated process.

Die Visual Inspection
100% of all outgoing die are inspected at 100x magnification. All inspections take place in a clean room area under a laminar flow hood.

Pack and Ship
Gel-Paks are packed and sealed in moisture barrier bags, boxed, and shipped to the customer. Each Gel-Pak is labeled with the device name, quantity of die, Alt and/or FPO number for traceability.

Statistical Bin Limits (SBL's)
SBL's are implemeted at the identified process steps to identify excursion material. An engineering disposition is required. See Section 4 for more details on SBL's.

Note 2: *= Statistical Bin Limits Implemented

Wafer Fab
Wafers for SmartDie products are fabricated on standard Intel fabrication processes. They are identical to wafers that are used for packaged products.

Sort 1
Standard Intel wafer level electrical test. Sort 1 is done at high temperatures.

Bake
An high temperature retention bake is performed to determine data retention capabilities of Flash devices. A typical bake is done at 250°C for 72 hours to accelerate normal customer usage conditions.

Sort 2
Standard Intel wafer level electrical test. Sort 2 is done at room temperature.

SmartSort
SmartSort is a wafer level sort which tests SmartSort product to the same criteria as packaged products including full speed AC/DC testing, 0-80°C temperature range (junction), same high levels of fault coverage, and reliability screens. The product is tested to data sheet parameters.

Wafer Saw
Die singulation process.

Gel-Pak Load
Good die are removed from the film frame and accurately placed in carbon conductive Gel-Paks.

Die Visual Inspection
100% of all outgoing die are inspected at 100x magnification. All inspections take place in a clean room area under a laminar flow hood.

Pack and Ship
Gel-Paks are packed and sealed in moisture barrier bags, boxed, and sent to the customer. Each Gel-Pak is labeled with the device name, quantity of die, Alt and/or FPO number for traceability. See section 4 for more information on traceability

Statistical Bin Limits (SBL's)
SBL's are implemeted at the identified process steps to identify excursion material. An engineering disposition is required. See Section 4 for more details on SBL's.