i960(R) Processors-Application Notes

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Commercial
	All
		AB-42--80960 Self-Test
		AP-733 Switched Ethernet Reference Design Description
		Consideration For Building Target Hardware For Use With MON960
		How ic960 R3.5 Handles 80960CA Branch Prediction Fot If-Then Conditionals
		Unexpected Float to Double Promotion in iC960 R3.0 and R3.5
		Using the iC960's R3.0/R3.5 Compiler's and Linker's Verbose Warning Switches as Debug Aids
		Using the MON960 System Calls, appl_exit_user and appl_go_user
	CX
		80960CX/80960JX/80960HX Architectural Comparison
		AP-506: Designing for 80960Cx and 80960Hx Compatibility
		AP-703: DRAM Controller for 33 MHz i960(R) CA/CF Microprocessors
		AP-704: A Simple DRAM Controller for 25/16 MHz i960® CA/CF Microprocessors
		AP-706: DRAM Controller for 40 MHz i960® CA/CF Microprocessors
	HX
		80960CX/80960JX/80960HX Architectural Comparison
		80960Hx Processor Initialization: IBR Fetching / Internal Initialization Sequence
		AP-506: Designing for 80960Cx and 80960Hx Compatibility
	JX
		80960CX/80960JX/80960HX Architectural Comparison
		AP-712: DRAM Controller for i960® JA/JF/JD Microprocessors
		Interfacing the i960(R)JX Microprocessor to the NEC uPD98401 * Local ATM Segmentation and Reassembly (SAR) Chip
	RX
		AP-732: I/O APIC Emulation Software for the i960(R) RP Microprocessor
		Intelligent I/O in the PC-Based Enterprise Computing Environment