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80960Hx Processor Initialization: IBR Fetching / Internal Initialization Sequence


ABSTRACT

Intel's i960® HA/HD/HT processor (abbreviated "Hx") user's manual provides only a functional description of the processor's initialization process, not an external bus behavior description. Users need to know what to expect on a logic analyzer trace during processor initialization, especially in the early stages of hardware or software debugging. This document describes how the Hx address and data buses behave during initialization, from the first IBR fetch through the first user code fetch.

This paper supplements the initialization information found in chapters 14 and 15 of the i960® Hx Microprocessor User's Manual.

TOPICS COVERED IN THIS DOCUMENT

TOPICPg.DESCRIPTION
THE INITIAL MEMORY IMAGE (IMI)2Review of the boot data structures
SELF TEST2External behavior during self test
FETCHING THE IBR2Initial bus configuration and bus confidence test
INITIALIZING INTERNAL REGISTERS5Processor initialization bus sequence
REFERENCES6Other places to read

THE INITIAL MEMORY IMAGE (IMI)

During initialization, the Hx reads a set of register and pointer values from external memory and caches them on-chip. Collectively, these values are called the Initial Memory Image (IMI). The IMI values are organized into the following six data structures:

The IMI typically resides in user ROM located in memory region 15.

SELF TEST

If self test is enabled (the STEST pin held high) when the RESET# pin goes high, the Hx executes internal self test immediately. No external memory accesses occur. Though changing values may appear on the address bus, the ADS# pin never toggles to initiate an external memory access.

Regardless whether self test is enabled or not, the FAIL# pin remains low after reset, then toggles high briefly before proceeding to the external bus confidence test.

FETCHING THE IBR

After passing self test, the processor runs an external bus confidence test, which checks external bus functionality. This test fetches the last eight words from the Initialization Boot Record (IBR) and performs a checksum on the words (for more detailed information on the checksum, see Chapter 14 in the i960®Ò Hx Microprocessor User's Manual).

Before fetching the last eight words, the Hx fetches memory configuration data for memory region 15 (0xF0000000 - 0xFFFFFFFF) from the first four words of the IBR. This memory configuration applies only during initialization; it is superseded later when the external Control Table is loaded.

Tables 1, 2, and 3 show the address and data bus activity the user should see for 8-, 16-, and 32-bit memory regions, respectively.

Table 1: Address and Data Bus for an IBR Fetch from an 8-Bit Boot Region

Memory AddressDataAccess Type
0xFEFFFF30PMCON15, byte 0Single byte access
0xFEFFFF38PMCON15, byte 2Single byte access
0xFEFFFF34PMCON15, byte 1Single byte access
0xFEFFFF3CPMCON15, byte 3Single byte access
0xFEFFFF40First Instruction Pointer (IP)Burst of 4 bytes
0xFEFFFF44PRCB PointerBurst of 4 bytes
0xFEFFFF48Bus Confidence Self-Test Check Word 0Burst of 4 bytes
0xFEFFFF4CBus Confidence Self-Test Check Word 1Burst of 4 bytes
0xFEFFFF50Bus Confidence Self-Test Check Word 2Burst of 4 bytes
0xFEFFFF54Bus Confidence Self-Test Check Word 3Burst of 4 bytes
0xFEFFFF58Bus Confidence Self-Test Check Word 4Burst of 4 bytes
0xFEFFFF5CBus Confidence Self-Test Check Word 5Burst of 4 bytes

Table 2: Address and Data Bus for an IBR Fetch from a 16-Bit Boot Region

Memory AddressDataAccess Type
0xFEFFFF30PMCON15, byte 0Single byte access
0xFEFFFF38PMCON15, byte 2Single byte access
0xFEFFFF34PMCON15, byte 1Single byte access
0xFEFFFF3CPMCON15, byte 3Single byte access
0xFEFFFF40First Instruction Pointer (IP)Burst of 2 half-words
0xFEFFFF44PRCB PointerBurst of 2 half-words
0xFEFFFF48Bus Confidence Self-Test Check Word 0Burst of 2 half-words
0xFEFFFF4CBus Confidence Self-Test Check Word 1Burst of 2 half-words
0xFEFFFF50Bus Confidence Self-Test Check Word 2Burst of 2 half-words
0xFEFFFF54Bus Confidence Self-Test Check Word 3Burst of 2 half-words
0xFEFFFF58Bus Confidence Self-Test Check Word 4Burst of 2 half-words
0xFEFFFF5CBus Confidence Self-Test Check Word 5Burst of 2 half-words

Table 3: Address and Data Bus for an IBR Fetch from a 32-Bit Boot Region

Memory AddressDataAccess Type
0xFEFFFF30PMCON15, byte 0Single byte access
0xFEFFFF38PMCON15, byte 2Single byte access
0xFEFFFF34PMCON15, byte 1Single byte access
0xFEFFFF3CPMCON15, byte 3Single byte access
0xFEFFFF40First Instruction Pointer (IP)Single word access
0xFEFFFF44PRCB PointerSingle word access
0xFEFFFF48Bus Confidence Self-Test Check Word 0Single word access
0xFEFFFF4CBus Confidence Self-Test Check Word 1Single word access
0xFEFFFF50Bus Confidence Self-Test Check Word 2Single word access
0xFEFFFF54Bus Confidence Self-Test Check Word 3Single word access
0xFEFFFF58Bus Confidence Self-Test Check Word 4Single word access
0xFEFFFF5CBus Confidence Self-Test Check Word 5Single word access

INITIALIZING INTERNAL REGISTERS

After the Hx processor finishes fetching the IBR (assuming it passed the external bus confidence test), it starts filling its internal tables and registers. Using the PRCB pointer from the IBR, the Hx begins reading data from the Interrupt Table, the System Procedure Table, and the Control Table. Table 4 lists the fetching address order and corresponding data.

Table 4: Processor Fetching Between the IBR and User Code

Relative Memory AddressDataData Size
prcb_ptr + 0x0Fault Table Base Address1 word
prcb_ptr + 0x4Control Table Base Address1 word
prcb_ptr + 0x8AC Register Initial Image1 word
prcb_ptr + 0xCFault Configuration Word1 word
prcb_ptr + 0x10Interrupt Table Base Address1 word
prcb_ptr + 0x14System Procedure Table Base Address1 word
prcb_ptr + 0x1CInterrupt Stack Pointer1 word
prcb_ptr + 0x20Instruction Cache Configuration Word1 word
prcb_ptr + 0x24Register Cache Configuration Word1 word
int_tbl_ptr + 0x3E4NMI Vector #1 word
sys_proc_tbl_ptr + 0xCSupervisor Stack Pointer Base1 word
ctrl_tbl_ptr + 0x10Interrupt Map 0 (IMAP0)1 word
ctrl_tbl_ptr + 0x14Interrupt Map 1 (IMAP1)1 word
ctrl_tbl_ptr + 0x18Interrupt Map 2 (IMAP2)1 word
ctrl_tbl_ptr + 0x1CInterrupt Control (ICON)1 word
ctrl_tbl_ptr + 0x20PMCON01 word
ctrl_tbl_ptr + 0x24PMCON11 word
ctrl_tbl_ptr + 0x28PMCON21 word
ctrl_tbl_ptr + 0x2CPMCON31 word
ctrl_tbl_ptr + 0x30PMCON41 word
ctrl_tbl_ptr + 0x34PMCON51 word
ctrl_tbl_ptr + 0x38PMCON61 word
ctrl_tbl_ptr + 0x3CPMCON71 word
ctrl_tbl_ptr + 0x40PMCON81 word
ctrl_tbl_ptr + 0x44PMCON91 word
ctrl_tbl_ptr + 0x48PMCON101 word
ctrl_tbl_ptr + 0x4CPMCON111 word
ctrl_tbl_ptr + 0x50PMCON121 word
ctrl_tbl_ptr + 0x54PMCON131 word
ctrl_tbl_ptr + 0x58PMCON141 word
ctrl_tbl_ptr + 0x5CPMCON151 word
ctrl_tbl_ptr + 0x68Trace Controls (TC)1 word
ctrl_tbl_ptr + 0x6CBus Configuration Control (BCON)1 word
IPStart Fetching User Code1 word

Once the Hx finishes fetching the pertinent information from the Initial Memory Image (IMI), it uses the Instruction Pointer (IP) from the IBR to start fetching user code. Processor-initiated initialization is complete at this point. The user code is then required to execute the rest of the initialization as outlined in the initialization code provided in the user's manual.

REFERENCES

The following documents provide more information on the i960® Hx microprocessor family.

1. i960® Hx Microprocessor User's Manual, Intel order number 272484. Pre-production draft copies are available from your Intel representative, listed in the back of any Intel data book or user's manual.

2. 80960HA/HD/HT Embedded 32-bit Microprocessor Advance Data Sheet, order number 272495. Also available in the i960® Processors and Related Products handbook, Intel order number 272084.

3. Designing for 80960Cx and 80960Hx Compatibility, Application Note AP-506, Intel order number 272556. Also available in the i960® Processors and Related Products handbook, order number 272084.



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