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Intel's i960® HA/HD/HT processor (abbreviated "Hx") user's manual provides only a functional description of the processor's initialization process, not an external bus behavior description. Users need to know what to expect on a logic analyzer trace during processor initialization, especially in the early stages of hardware or software debugging. This document describes how the Hx address and data buses behave during initialization, from the first IBR fetch through the first user code fetch.
This paper supplements the initialization information found in chapters 14 and 15 of the i960® Hx Microprocessor User's Manual.
| TOPIC | Pg. | DESCRIPTION |
| THE INITIAL MEMORY IMAGE (IMI) | 2 | Review of the boot data structures |
| SELF TEST | 2 | External behavior during self test |
| FETCHING THE IBR | 2 | Initial bus configuration and bus confidence test |
| INITIALIZING INTERNAL REGISTERS | 5 | Processor initialization bus sequence |
| REFERENCES | 6 | Other places to read |
During initialization, the Hx reads a set of register and pointer values from external memory and caches them on-chip. Collectively, these values are called the Initial Memory Image (IMI). The IMI values are organized into the following six data structures:
If self test is enabled (the STEST pin held high) when the RESET# pin goes high, the Hx executes internal self test immediately. No external memory accesses occur. Though changing values may appear on the address bus, the ADS# pin never toggles to initiate an external memory access.
Regardless whether self test is enabled or not, the FAIL# pin remains low after reset, then toggles high briefly before proceeding to the external bus confidence test.
After passing self test, the processor runs an external bus confidence test, which checks external bus functionality. This test fetches the last eight words from the Initialization Boot Record (IBR) and performs a checksum on the words (for more detailed information on the checksum, see Chapter 14 in the i960®Ò Hx Microprocessor User's Manual).
Before fetching the last eight words, the Hx fetches memory configuration data for memory region 15 (0xF0000000 - 0xFFFFFFFF) from the first four words of the IBR. This memory configuration applies only during initialization; it is superseded later when the external Control Table is loaded.
Tables 1, 2, and 3 show the address and data bus activity the user should see for 8-, 16-, and 32-bit memory regions, respectively.
| Memory Address | Data | Access Type |
| 0xFEFFFF30 | PMCON15, byte 0 | Single byte access |
| 0xFEFFFF38 | PMCON15, byte 2 | Single byte access |
| 0xFEFFFF34 | PMCON15, byte 1 | Single byte access |
| 0xFEFFFF3C | PMCON15, byte 3 | Single byte access |
| 0xFEFFFF40 | First Instruction Pointer (IP) | Burst of 4 bytes |
| 0xFEFFFF44 | PRCB Pointer | Burst of 4 bytes |
| 0xFEFFFF48 | Bus Confidence Self-Test Check Word 0 | Burst of 4 bytes |
| 0xFEFFFF4C | Bus Confidence Self-Test Check Word 1 | Burst of 4 bytes |
| 0xFEFFFF50 | Bus Confidence Self-Test Check Word 2 | Burst of 4 bytes |
| 0xFEFFFF54 | Bus Confidence Self-Test Check Word 3 | Burst of 4 bytes |
| 0xFEFFFF58 | Bus Confidence Self-Test Check Word 4 | Burst of 4 bytes |
| 0xFEFFFF5C | Bus Confidence Self-Test Check Word 5 | Burst of 4 bytes |
Table 2: Address and Data Bus for an IBR Fetch from a 16-Bit Boot Region
| Memory Address | Data | Access Type |
| 0xFEFFFF30 | PMCON15, byte 0 | Single byte access |
| 0xFEFFFF38 | PMCON15, byte 2 | Single byte access |
| 0xFEFFFF34 | PMCON15, byte 1 | Single byte access |
| 0xFEFFFF3C | PMCON15, byte 3 | Single byte access |
| 0xFEFFFF40 | First Instruction Pointer (IP) | Burst of 2 half-words |
| 0xFEFFFF44 | PRCB Pointer | Burst of 2 half-words |
| 0xFEFFFF48 | Bus Confidence Self-Test Check Word 0 | Burst of 2 half-words |
| 0xFEFFFF4C | Bus Confidence Self-Test Check Word 1 | Burst of 2 half-words |
| 0xFEFFFF50 | Bus Confidence Self-Test Check Word 2 | Burst of 2 half-words |
| 0xFEFFFF54 | Bus Confidence Self-Test Check Word 3 | Burst of 2 half-words |
| 0xFEFFFF58 | Bus Confidence Self-Test Check Word 4 | Burst of 2 half-words |
| 0xFEFFFF5C | Bus Confidence Self-Test Check Word 5 | Burst of 2 half-words |
Table 3: Address and Data Bus for an IBR Fetch from a 32-Bit Boot Region
| Memory Address | Data | Access Type |
| 0xFEFFFF30 | PMCON15, byte 0 | Single byte access |
| 0xFEFFFF38 | PMCON15, byte 2 | Single byte access |
| 0xFEFFFF34 | PMCON15, byte 1 | Single byte access |
| 0xFEFFFF3C | PMCON15, byte 3 | Single byte access |
| 0xFEFFFF40 | First Instruction Pointer (IP) | Single word access |
| 0xFEFFFF44 | PRCB Pointer | Single word access |
| 0xFEFFFF48 | Bus Confidence Self-Test Check Word 0 | Single word access |
| 0xFEFFFF4C | Bus Confidence Self-Test Check Word 1 | Single word access |
| 0xFEFFFF50 | Bus Confidence Self-Test Check Word 2 | Single word access |
| 0xFEFFFF54 | Bus Confidence Self-Test Check Word 3 | Single word access |
| 0xFEFFFF58 | Bus Confidence Self-Test Check Word 4 | Single word access |
| 0xFEFFFF5C | Bus Confidence Self-Test Check Word 5 | Single word access |
After the Hx processor finishes fetching the IBR (assuming it passed the external bus confidence test), it starts filling its internal tables and registers. Using the PRCB pointer from the IBR, the Hx begins reading data from the Interrupt Table, the System Procedure Table, and the Control Table. Table 4 lists the fetching address order and corresponding data.
| Relative Memory Address | Data | Data Size |
| prcb_ptr + 0x0 | Fault Table Base Address | 1 word |
| prcb_ptr + 0x4 | Control Table Base Address | 1 word |
| prcb_ptr + 0x8 | AC Register Initial Image | 1 word |
| prcb_ptr + 0xC | Fault Configuration Word | 1 word |
| prcb_ptr + 0x10 | Interrupt Table Base Address | 1 word |
| prcb_ptr + 0x14 | System Procedure Table Base Address | 1 word |
| prcb_ptr + 0x1C | Interrupt Stack Pointer | 1 word |
| prcb_ptr + 0x20 | Instruction Cache Configuration Word | 1 word |
| prcb_ptr + 0x24 | Register Cache Configuration Word | 1 word |
| int_tbl_ptr + 0x3E4 | NMI Vector # | 1 word |
| sys_proc_tbl_ptr + 0xC | Supervisor Stack Pointer Base | 1 word |
| ctrl_tbl_ptr + 0x10 | Interrupt Map 0 (IMAP0) | 1 word |
| ctrl_tbl_ptr + 0x14 | Interrupt Map 1 (IMAP1) | 1 word |
| ctrl_tbl_ptr + 0x18 | Interrupt Map 2 (IMAP2) | 1 word |
| ctrl_tbl_ptr + 0x1C | Interrupt Control (ICON) | 1 word |
| ctrl_tbl_ptr + 0x20 | PMCON0 | 1 word |
| ctrl_tbl_ptr + 0x24 | PMCON1 | 1 word |
| ctrl_tbl_ptr + 0x28 | PMCON2 | 1 word |
| ctrl_tbl_ptr + 0x2C | PMCON3 | 1 word |
| ctrl_tbl_ptr + 0x30 | PMCON4 | 1 word |
| ctrl_tbl_ptr + 0x34 | PMCON5 | 1 word |
| ctrl_tbl_ptr + 0x38 | PMCON6 | 1 word |
| ctrl_tbl_ptr + 0x3C | PMCON7 | 1 word |
| ctrl_tbl_ptr + 0x40 | PMCON8 | 1 word |
| ctrl_tbl_ptr + 0x44 | PMCON9 | 1 word |
| ctrl_tbl_ptr + 0x48 | PMCON10 | 1 word |
| ctrl_tbl_ptr + 0x4C | PMCON11 | 1 word |
| ctrl_tbl_ptr + 0x50 | PMCON12 | 1 word |
| ctrl_tbl_ptr + 0x54 | PMCON13 | 1 word |
| ctrl_tbl_ptr + 0x58 | PMCON14 | 1 word |
| ctrl_tbl_ptr + 0x5C | PMCON15 | 1 word |
| ctrl_tbl_ptr + 0x68 | Trace Controls (TC) | 1 word |
| ctrl_tbl_ptr + 0x6C | Bus Configuration Control (BCON) | 1 word |
| IP | Start Fetching User Code | 1 word |
Once the Hx finishes fetching the pertinent information from the Initial Memory Image (IMI), it uses the Instruction Pointer (IP) from the IBR to start fetching user code. Processor-initiated initialization is complete at this point. The user code is then required to execute the rest of the initialization as outlined in the initialization code provided in the user's manual.
The following documents provide more information on the i960® Hx microprocessor family.
1. i960® Hx Microprocessor User's Manual, Intel order number 272484. Pre-production draft copies are available from your Intel representative, listed in the back of any Intel data book or user's manual.
2. 80960HA/HD/HT Embedded 32-bit Microprocessor Advance Data Sheet, order number 272495. Also available in the i960® Processors and Related Products handbook, Intel order number 272084.
3. Designing for 80960Cx and 80960Hx Compatibility, Application Note AP-506, Intel order number 272556. Also available in the i960® Processors and Related Products handbook, order number 272084.
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