8x930Ax Universal Serial Bus Controller

Product Overview
The Intel 8x930Ax is a single chip Universal Serial Bus 1.0 specification compliant micro-controller. The motivation for USB comes from three interrelated considerations:

• Connection of the PC to the telephone
• Ease of use
• Port expansion

Installation of computer peripherals has always been a difficult task, but now plug and play is being brought outside the box, giving maximum flexibility to reconfigure and attach external peripherals to the PC.

The USB topology has three elements: host, hubs and functions. The PC is the host and the peripherals are the functions which need to interface via the USB to the PC; this is where the 8x930Ax comes in. The 8x930Ax is an 8-bit microcontroller designed specifically for USB peripherals based on the MCS® 251 microcontroller architecture. It is the first USB microcontroller in a roadmap planned to include other Intel architectures and features throughout 1996 and beyond.

USB defines four transfer types in order to enable a variety of peripherals: Control, Isochronous, Interrupt and Bulk. Every peripheral will need to support control transfers for configuration, command and status information flows between the host and peripheral. Isochronous transfers provide guaranteed bus access, constant data rate and error tolerance for devices such as CTI (computer-telephone integration) and audio systems. Interrupt transfers were designed to support human input devices such as joysticks, mice and keyboards that need to communicate small amounts of data infrequently, but with bounded service periods. Bulk transfers enable devices like printers, scanners and digital cameras to communicate large amounts of data to the PC as bus bandwidth becomes available.

Since USB enables such a wide variety of PC peripherals, the 8x930Ax and future proliferations will be found in the devices mentioned above as well as many others. USB could even bring about many new peripherals for the next generation of entertainment and productivity applications.

Product Description
The MCS 251 microcontroller architecture brings high performance, ample memory mix and addressing, low power, low noise, efficient high-level language support, enhanced instruction set, integrated features and functionality to the 8x930Ax.

The 8x930Ax has 1 Kbyte or 512 bytes of on-chip data RAM and is available ROMless or with 8Kbytes ROM or 16Kbytes ROM options. The 8x930Ax has up to 256Kbytes of external code/data memory space and 40 bytes of general purpose registers which reside in the CPU as register file. There are 16 possible byte registers, 16 possible word registers and 10 possible Dword registers in the register file depending on the combinations used.

Interfacing to external memory has the flexibility of adding up to 3 wait states or the real time wait function can be used to generate more wait states, allowing the use of slower memory devices. External instruction fetches can increase performance by 2x using Page mode which swaps the data onto the high byte of the address.

Code for the 8x930Ax can use either the MCS 51 or MCS 251 microcontroller instruction set. This gives the user the option to protect their software investment or gain maximum performance in their application.

The 8x930Ax features a rich combination of integrated peripherals that make it an even more powerful micro-controller. The Programmable Counter Array (PCA) provides the flexibility for applications that require real time compare/capture, high speed I/O and pulse width modulation capabilities. Also included is an enhanced serial port, three 16-bit timer/counters, a hardware watchdog timer, four 8-bit I/O ports and two power-saving modes: idle and power down.

USB Interface
The implementation of USB on the 8x930Ax can be divided into four sections: FIFOs, Function Interface Unit, Serial Bus Interface Engine and the transceiver.

The 8x930Ax has a total of eight FIFOs (first in, first out): four transmit FIFOs and four receive FIFOs. The four transmit/receive FIFOs support four function endpoints (0–3). Endpoint 0 is 16 bytes and is dedicated for control transfers. Endpoint 1 is user configurable up to 1024 bytes, and Endpoints 2 and 3 are 16 bytes; these endpoints can be used for interrupt, isochronous or bulk transfer types.

The transmit and receive FIFOs are circulating FIFOs which support up to two separate data sets of variable sizes and contain byte count registers that access the number of bytes in the data sets. They also have flags that detect a full or empty FIFO and have the capability of retransmitting or re-receiving the current data set.The 8x930Ax has three interrupts associated with USB: any start of frame, transmit/receive done for function endpoints and global suspend/resume.

The Function Interface Unit (FIU) manages the USB data that is received and transmitted based on the transfer type and the state of the FIFOs, and it includes monitoring the transaction status, managing the FIFOs, and relaying control events to the 8x930Ax CPU via interrupt requests.

The Serial Bus Interface Engine (SIE) handles the com-munication protocol of USB by packet sequencing, signal generation/detection, CRC generation/checking, NRZI data encoding/decoding, bit-stuffing and packet ID (PID) generation/decoding.

The USB cable consists of only four wires: Vbus, D+, D-, and GND. The data is differentially driven over D+ and D- at a full-speed signaling bit rate of 12 Mb/s or a low-speed signaling mode of 1.5 Mb/s. The transceiver is built on-chip, therefore no external circuitry is needed except for the pull-up terminating resistor on either the D+ or D- line to determine whether it's a full-speed or low-speed device.

Development Tools
Intel's USB product line has a complete development tools solution featuring a USB Evaluation Kit and a Peripheral Development Kit (PDK). The USB Evaluation Kit consists of an evaluation board plus an evaluation board manual, development tools from tool vendors, and a 8x930Ax user's manual. The PDK consists of a host system with Windows* 95 based utilities. These two offerings are available separately.

Key Features

Complete Universal Serial Bus 1.0 Specification compatibility - Supports Isochronous and Non-isochronous data - Bi-directional half-duplex link On-chip USB transceiver Serial Bus Interface Engine (SIE) - Packet decoding/generation - CRC generation and checking - NRZI encoding/decoding and bit-stuffing Four transmit FIFOs - Three 16-byte FIFOs - One configurable FIFO (up to 1Kbyte) Four receive FIFOs - Three 16-byte FIFOs - One configurable FIFO (up to 1Kbyte) Automatic transmit/receive FIFO management Suspend/Resume Operation Three new USB Interrupt vectors - USB Function Interrupt - Start of Frame - Suspend/Resume Phase lock loop - 12 Mbps or 1.5 Mbps data rate Low clock mode 256-Kbyte External Code/Data memory space Power-saving Idle and Powerdown modes User-selectable configurations - External wait state - Address range - Page mode	Real Time Wait Function 512 byte or 1 Kbyte on-chip data RAM On-chip ROM Options - ROMless, 8 Kbyte or 16 Kbyte Four input/output ports - 1 open drain port - 3 quasi bi-directional ports Programmable Counter Array (PCA) - 5 capture/compare modules Industry Standard MCS 51 microcontroller UART Hardware watchdog timer Three flexible 16-bit timer/counters Code compatibility with MCS 51 and MCS 251 microcontrollers Register-based MCS 251 microcontroller architecture - 40-byte register file - Registers accessible as bytes, words, or double words 6 or 12 MHz operation