• The Compelling Need for I/O Innovation
• PCI Breaks the Bus Bottleneck
• Examples of Intelligent I/O Innovation
• How the i960 Processor Powers a New Wave of I/O Innovation

Today's computing environment is changing rapidly along many dimensions. The increased performance levels of today's microprocessors highlight one major area in need of innovation -- data input/output (I/O) paths to and from the servers in the clients/server model. Innovative I/O designs are required because:

• Networked computing usage is replacing the stand-alone computing model, which in turn drives the need for network computing I/O.
• Networked computers increasingly aggregate vast quantities of data at the powerful server systems.
• Since the host processors (CPUs) in these servers now also run user applications, they need more powerful storage interfaces for accessing larger and larger disk storage areas.
• Simultaneously, the sizes of files and messages are exploding as users move from simple ASCII data messages to complex, typeset-quality documents. These documents increasingly contain natural data elements like video or audio that require huge file sizes.

Clearly, in today's client/server model, aggregated data congestion occurs more frequently at the servers. As server OEMs seek to tap rapid growth in applications servers, they need to develop I/O performance levels commensurate with today's host CPU performance levels.

The Intel architecture continues to double performance every 18 months.

This is no easy task, since the Intel Architecture continues to double performance every 18 months! With multiprocessing on the horizon, the issue of balance between server performance and that of the data I/O paths becomes even more critical.

PCI Breaks the Bus Bottleneck
Host CPUs get data to and from I/O adapters via the system bus. The system bus has a tremendous impact on overall system performance as it defines the maximum bandwidth and the flexibility and effectiveness of data transfers. Fortunately for today's server architects, the Peripheral Component Interconnect (PCI) bus acceptance level has grown from its original intended use as a local bus to industry-wide use as an I/O expansion bus.

The PCI bus features enable intelligent I/O subsystems to contribute to increased system performance and superior balance between applications processing and I/O handling.

The PCI bus was defined to provide the much needed bandwidth expansion over its predecessors: EISA, ISA, and MCA. At 132 Mbytes/second, PCI provides more than four times the EISA bus bandwidth and an even more dramatic performance improvement when compared to the popular ISA bus. More important to enabling I/O innovation are the features of PCI, which expand its flexibility and effectiveness as an I/O bus.

PCI Features Unleash the Power of I/O
System architects have long used intelligent I/O subsystems in proprietary server architectures to achieve balanced high performance. However, the non-proprietary buses (EISA, ISA, MCA) have offered little support for intelligent I/O, often diluting the value of I/O processors because of the lack of bus flexibility.

The PCI bus incorporates many advanced features that enable intelligent I/O subsystems to contribute to increased system performance and superior balance between applications processing and I/O handling. Consequently, PCI launches an era in which manufacturers can be innovative with intelligent I/O subsystems to offer high-performance open server platforms.

Several PCI feature provide the basis for new intelligent I/O solutions.

• First, the PCI bus provides for high-speed data bursting, enabling intelligent I/O subsystems to maximize the amount of data transferred for each bus-acquisition sequence.
• The PCI bus also supports the interleaving of accesses to system resources (i.e., host memory), so that intelligent I/O subsystems can more effectively operate in parallel with the host application task. This improves computing productivity.
• PCI allows for multiple bus masters so that intelligent I/O subsystems can send data traffic to each other (peer to peer) without requiring host CPU intervention to upload and re-copy the data to the target. Since PCI allows expansion through defined segments, peer-to-peer traffic can be isolated to a portion of the overall I/O bus, while concurrent transfers continue between another PCI segment and the host. This, too enhances productivity.

Examples of Intelligent I/O Innovation
Storage I/O Interfaces
In the two basic areas of server I/O, network and storage, there are examples in which intelligent I/O subsystems offer superior server performance possibilities.

One of the best-known examples is RAID controllers. In this application, the server can initiate a disk store or retrieve command as if it were writing to a single disk. The intelligent RAID controller separates the command into parallel read or write commands to its attached array of disks.

This parallel operation, controlled by the intelligent I/O processor, compensates for the single disk spin-up delay and protects data. This method results in superior data transfer rates as well as greater reliability, a critical necessity as servers become more widely used for corporate computing and the creation of databases.

A similar example of how intelligent I/O improves server storage connection is in caching disk controllers. In this application, the host can write a data file to the intelligent disk controller's cache at speeds matching the fast DRAM memory. The host is then free to continue application execution while the I/O processor controls the actual disk storage sequences. With an I/O processor, the caching algorithms can be fine-tuned to the specific application role of the target server (e.g., streaming for a video server).

Network I/O Interfaces
On the network I/O interface side, there are also many examples in which intelligent I/O subsystems provide the means to balance system performance and I/O capabilities.

In Ethernet and token ring LAN interfaces, I/O processors handle the frequent I/O interrupts and intelligently buffer messages to and from the host. This allows the host to streamline applications processing and to use other system resources such as the system bus and memory more effectively.

In WAN interfaces, intelligent I/O processing also allows significant performance improvements. For example, intelligent WAN interfaces can compress large message files prior to transmission. This not only frees the host CPU to perform more valuable applications tasks, but can allow more users to share the same fixed, wide-area connection (currently fixed at a painfully slow 1.5 Mbits/second).

Emerging Interface Technologies
In both storage and network interfaces, new intelligent I/O approaches will shrink the time-to-market for newer, high-performance interfaces. As new interfaces are defined, they are often useable before there is industry-wide agreement on all aspects of the interface implementation. However, server buyers often forego the performance benefits of breakthrough technological advances because they fear costly hardware changes when interface implementations do become standardized.

Intelligent I/O applications, however, obviate this fear with the software programmability of the appropriate interface elements.

For example, the next-generation network interface, asynchronous transfer mode (ATM), trend-setter companies like Fore Systems have used an intelligent adapter architecture to implement flow control. Users have been able to take advantage of these adapters while the ATM Forum considers flow control standards. As these standards solidify, Fore Systems offers its customers the capability to gain compliance easily via a software update to the I/O processor.

The same benefits apply to storage interfaces. For example, early-adopter Fibre Channel suppliers are speeding adoption by offering intelligent I/O solutions that will evolve to support maturing standards.

How the i960 Processor Powers a New Wave of I/O Innovation
Low-Cost MIPS
As the price per MIPS of 32-bit embedded processing has fallen, lower prices have become the catalyst for significant system innovation. In imaging applications, for example, the transition from 16-bit to 32-bit embedded processors has enabled manufacturers to reach near typeset-quality laser-printed document while slashing laser printer prices.

This unique combination of a robust, widely accepted PCI bus and low-cost embedded I/O processing creates a tremendously fertile environment for I/O innovation.

As the new era of intelligent I/O begins, innovators can get leading edge 32-bit embedded processors for prices far lower than when they defined their previous-generation EISA or MCA bus products. Because the PCI bus features allow for greater concurrency, each I/O processor MIPS provides a more meaningful contribution to overall system performance.

This unique combination of a robust, widely accepted PCI bus and low-cost embedded I/O processing creates a tremendously fertile environment for I/O innovation.

Architecture Roadmap Importance
The i960 processor became the leading 32-bit RISC processor by leading the industry down the $/MIPS curve and by supporting designers with a wide range of development tools.

As I/O innovators consider applying 32-bit RISC power to their product plans they must also consider the ability to track the performance of the host processor in the target server system. Because the i960 CPUs are on the same technology track as Intel Architecture host CPUs, I/O innovators are assured that the architecture will have higher performance processor implementation for their subsequent product generations.

More Than a Processor
The i960 processor family today offers the most complete set of PCI building blocks for the new wave of innovative I/O products.

For more information on this SDK, see the PCI Software Development Kit section.

Intel offers a complete i960 Processor PCI Software Development Kit (SDK) specifically for I/O innovators. This SDK allows developers to begin I/O interface code development quickly and easily. The SDK contains everything necessary to start developing in a PCI system, including compiler, debugger, monitor, and the base board.

The stand-alone board offers user-selectable, interchangeable i960 processor modules. The developer can choose the processor version that best matches the I/O application. With performance ranging from 10 to 150 MIPS, i960 processors provide the scalability to match the tremendous range of I/O interface speeds and complexities (e.g., 25 Mbits/second to 622 Mbits/second ATM).

All i960 processors are software-compatible.

Contributing to the kit's flexibility are products from another Solutions960 program partner, Cyclone Microsystems, whose I/O interface modules allow the developer to select from an assortment of I/O interface modules the one most suitable for a given I/O application. Software development can then begin in an environment very much like that for which the I/O product is being developed.

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