![[INTEL NAVIGATION HEADER]](../../PIX/HEADER.GIF){kind=small}
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Intel PCIsets include a system controller, data path units and the 82371SB PCI IDE/ISA Xcelerator (PIIX3).  The PCIset forms a host-to-PCI bridge and provides L2 cache control and a full-function 64-bit data path to main memory.
The B-0 stepping of the PIIX3 provides a bridge between the PCI bus and the ISA bus and contains the Universal Serial Bus host controller. The USB controller offers full compatibility with the Universal Host Controller Interface (UHCI) and includes the Serial Interface Engine (SIE). The B-0 stepping of the PIIX3 can be identified by the marking SB,82371SB S U093.
The SIE handles the USB communication protocol by packet sequencing, signal generation/detection, CRC generation/checking, NRZI data encoding, bit-stuffing and packet ID (PID) generation/decoding.
A partial list of PIIX3 B-0 stepping performance features:
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