This application note describes the interface between Intel's i960 ® JA/JF/JD microprocessors and NEC's uPD98401 ® Local ATM Segmentation And Reassembly (SAR) Chip, with 2 Mbytes of DRAM available to the i960 Jx processor. The interface provides for single and burst reads/writes to the DRAM and single reads and writes to the SAR chip, using the i960 Jx processor configured with a 32-bit bus. The interface is controlled by a DRAM controller and a SAR controller.
This document discusses DRAM controller theory with interleaving, and a basic slave read/write controller to the SAR. It also describes the supporting state machines, timing diagrams, and PLD equations.
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27277901.pdf
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