Speedwave*

SpeedWave* is a complete, easy to use, high-performance, interactive, IEEE 1076 VHDL simulation system. With its native VHDL source code debugger, this powerful tool allows for quick analysis and debug of complex designs. Integrated with SpeedWave is a fully featured, easy-to-
use waveform display for digital simulation. Viewing simulation results as waveforms speed the debug of designs, decreasing the amount of time required to move a design from conception to physical implementation.
SpeedWave is an interactive, event-driven, digital simulator. Its extremely versatile evaluation mechanism uses the complete IEEE 1076 VHDL language for defining arbitrary states and strengths. SpeedWave also supports a unique 28-state algorithm to assure high speed and high
accuracy evaluation of structural designs.
Simulation debugging is a seamless part of this environment, offering both structural gate level and VHDL based debugging. Not only is Viewlogic's VHDL debugger a true source-level debugger, it can also display individual sections of each source level statement, such as the signal update or process execution. An expandable watchpoint window is also available to allow the user to view anything in the design, whether it is a signal, VHDL variable, or event name. A powerful graphical navigator is also available that allows the user to view the design hierarchically,
navigating through schematic blocks or VHDL processes.