QuickBench*

QuickBench is a tool that creates dynamic self-checking behavioral models for use as components in a testbench. QuickBench combines the stimulus-response mechanism in dynamic testbenches with the automatic monitoring and error-flagging features in self-checking testbenches.
Creating models with QuickBench is easier, faster, and more accurate than coding them by hand because QuickBench lets you describe the interface behavior of the components using the original timing diagram specifications.
QuickBench automatically generates source code for VHDL entity/architectures or Verilog modules that implement the model of each component. A QuickBench component model includes everything that is necessary to perform the interface cycles described in the timing diagrams of that component.
QuickBench also provides an architecture for controlling the execution of interface cycles in QuickBench-generated models. The architecture supports a user-written top-level test sequence that uses QuickBench-generated subroutines to initiate and control the execution of interface cycles by QuickBench-generated components.
QuickBench supports interactive databooks from our Synchrony program. This allows you to begin your testbench development with existing intelligent timing diagrams, direct from-the-manufacturer.