This section describes the behavior of operating systems during context switching.

Different operating systems take different approaches for state-saving:

• Some operating systems save the entire floating-point state.
• Some save the floating-point state only when it is required.
• Some may save a partial floating-point state.

The existing task switch code for IA implementations (including floating-point code) does not change for systems that include MMX code.

4.1.1 Cooperative Multitasking Operating System

In a cooperative operating system, application tasks can predetermine when it is about to be switched out. Tasks can prepare in advance for the switch.

Application programmers must know whether the operating system performs a state save or whether it is their responsibility to perform a state save.

4.1.2 Preemptive Multitasking Operating System

In a preemptive multitasking operating system, the application cannot know when it is preempted. Applications cannot prepare in advance for task switching. The operating system is responsible for saving and restoring the state when necessary.

The IA MMX technology was defined to support the same state-saving and restoring techniques as the floating-point state-saving and restoring techniques. Existing operating systems can continue to run without modifications.

Figure 4­1 illustrates an example of an operating system implementing floating-point or MMX state saving.

Detecting when to save the FP or MMX state needs to be saved is the same process used for detecting when the floating-point state needs to be saved. If CR0.TS=1 (task switch bit in control register 0), then the next FP or MMX instruction generates exception Int 7.

1. The operating system maintains a save area for each task (Save Areas A and B in Figure 4­1).
2. It defines a variable that indicates which task "owns" the FP or MMX state.
3. On a task switch, the OS sets the CR0.TS to 1 if the incoming task does not own the FP or MMX state. Otherwise, it sets it to 0.
4. If a new task attempts to use an MMX instruction, (while CR0.TS=1), exception Int 7 is generated. The Int 7 handler ("owned" by the operating system) saves the FP or MMX state to the save area of the FP or MMX state owner and restores the FP or MMX state from the save area of the current task.
5. The ownership of the FP or MMX state then changes to the current task and CR0.TS=0.

Figure 4­1. Example of FP and MMX^TM Technology State Saving in Operating System

4.2 EXCEPTIONS

MMX instructions do not generate numeric exceptions or affect the processor architecture status flags. Previously pending floating-point numeric errors are reported.

The MMX instructions can generate the following exceptions:

• Memory access exceptions:
  #SS Interrupt 12 - Stack exception
  #GP Interrupt 13 - General Protection
  #PF Interrupt 14 - Page Fault
  #AC Interrupt 17 - Alignment Check, if enabled by CPU configuration.
• System exceptions:
  #UD Interrupt 6 - Invalid Opcode
  Executing an MMX instruction when CR0.EM=1 generates an Invalid Opcode exception.
  #NM Interrupt 7 - Device not available. The TS bit in CR0 is set.
• Pending floating-point error:
  #MF Interrupt 16 - Pending floating-point error
• Other exceptions that occur indirectly due to faulty execution of the above exceptions. For example: Interrupt 12 occurs due to MMX instructions, and the interrupt gate directs the processor to invalid TSS (task state segment).

The MMX instructions are accessible from all operation modes of IA: Protected mode, Real address mode, and Virtual 8086 mode.

4.3 COMPATIBILITY WITH EXISTING SOFTWARE ENVIRONMENTS

4.3.1 Register Aliasing

The MMX state is aliased on the floating-point state:

• MMX registers MM0-MM7 are aliased on the 64-bit mantissas of the floating-point register (See Figure 4­2).
• A value written to an MMX register using MMX instructions also appears in one of the eight floating-point registers (bits 63-0). The exponent field of the corresponding floating-point register (bits 78-64) and its sign bit (bit 79) are set to ones (11s).
• The mantissa of a floating-point value written to a floating-point register by floating-point instructions also appears in an MMX register.

Figure 4­2. Aliasing of MMX™ Technology to Floating-Point Registers

MMX registers map to the physical locations of floating-point registers. MMX register mapping is fixed and does not change when the TOS (Top Of Stack field in the floating-point status word, bits 11-13) changes.

The value of the TOS is set to 0 after each MMX instruction.

In the floating-point context, STn refers to the relative location of a FP register, n, to the TOS. However, the FP tag bits refer to the physical locations of the FP register. The MMX registers always refer to the physical location.

In Figure 4­3, the inner circle refers to the physical location of the FP and MMX^TM registers. The outer circle refers to FP register's relative location to the current TOS.

When the TOS=0 (case a in Figure 4­3), ST0 points to the physical location 0 on the floating-point stack. MM0 maps to ST0, MM1 maps to ST1, and so on.

When the TOS=2 (case b in Figure 4­3), ST0 points to the physical location 2. MM0 maps to ST6, MM1 maps to ST7, MM2 maps to ST0, and so on.

Figure 4­3. Mapping of MMX™ Registers to Floating Point Registers

4.3.2 The Effect of Floating-Point and MMX™ Instructions on the Floating-Point Tag Word

Using an MMX instruction (except EMMS) validates (sets to 00s) the entire floating-point tag word.

The EMMS instruction sets the entire FP tag bits register to empty (11s in each tag field).

FSAVE and FSTENV instructions read the FP tag word and store the contents of the FP tag word in memory. Executing these instructions calculates the precise values of the FP tag word fields based on the current contents of the registers. After executing these instructions, all tag bit values are valid for MMX instructions: Valid, Zero, Special, Empty. The value of the FP tag word does not affect the MMX registers or execution of MMX instructions.

Table 4­1 summarizes the effect of FP or MMX instructions and FSAVE/ FSTENV instructions on the tag bit fields in an FP or MMX register and defines their value in memory.

4.3.2.1 ALIASING SUMMARY

Table 4­2 summarizes the effects of the MMX^TM instructions on the floating-point state.

Note: MMn refers to one MMX register.

4.3.3 Context Switch Support

If the task switch bit (TS) in control register 0 (CR0) is set (CR0.TS=1), the first FP or MMX instruction that executes will trigger Int 7, Device not available (DNA). Causing a DNA fault enables an operating system to save the context of the FP or MMX registers with the same code currently used to save the FP state. Both the FSAVE (Store FP state) and FRSTOR (Restore FP state) instructions are used to save and restore either the FP or MMX state.

See Section X_ContextSwitching4.1. for more details on context switching.

4.3.4 Floating-Point Exceptions

When floating-point exceptions are enabled and a FP exception is pending, subsequent MMX instruction execution reports an FP error (Int 16 and/or FERR# signal). The pending exception is handled by the FP exception handler. Execution resumes at the interrupted MMX instruction.

Before the MMX instruction is executed, the FP state is maintained and is visible to the FP exception handler.

See Section 3.3.6 for more detail.

4.3.5 Debugging

The debug features for Intel Architecture implementations operate in the same manner on the MMX instruction set. This enables debuggers to debug code that uses the MMX technology.

4.3.6 Emulation of the Instruction Set

There is no emulation support for microprocessors that support the MMX technology.

The CR0.EM bit used to emulate floating-point instructions cannot be used in the same way for MMX instruction emulation. If an MMX instruction executes when the CR0.EM bit is set, an invalid opcode exception (Int 6) is generated.

4.3.7 Exception handling in Operating Systems

This section specifies system exceptions. Exception handling in MMX code is discussed in Section 3.3.6.

An invalid opcode exception (Int 6) can occur due to MMX instruction execution two cases:

• On implementations that do not support IA MMX technology.
• When CR0.EM=1 and an MMX instruction is executed.

The CR0.EM bit is used to emulate the FP instructions in software. In this case, the operating system does not save the FP hardware state on task switches and does not save the MMX state. An invalid opcode exception is generated to flag this event to the operating system, and prevent application errors from occurring.

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