Chapter 6
MMX™ TECHNOLOGY PERFORMANCE MONITORING EXTENSIONS

The most effective way to improve the performance of your code is to find the performance bottlenecks. Intel Architecture processors include a counter on the processor that will allow you to gather information about the performance of your application. This counter keeps track of events that occur while your code is executing. You can read the counter during execution and determine if your code has stalls. This may be accomplished by using Intel's VTune profiling tool or by using instructions within your code.

The section describes the performance monitoring features for MMX code on Pentium^® and P6-family processors with MMX technology.

The RDPMC instruction is described in Section 6.3.

6.1 Superscalar (Pentium® Family) Performance Monitoring Events

All Pentium processors feature performance counters and several new events have been added to support MMX technology. All new events are assigned to one of the two event counters (CTR0, CTR1), with the exception of "twin events" (such as " D1 starvation" and "FIFO is empty") which are assigned to different counters to allow their concurrent measurement. The events must be assigned to their specified counter. Table 6-1 lists the performance monitoring events. New events are listed in bold.

Table 6-1. Performance Monitoring Events

6.1.1 DESCRIPTION OF MMX^TM INSTRUCTION EVENTS

The event codes/counter are provided in parenthesis.

• MMX instructions executed in U-pipe (101011/0):
  -- Total number of MMX instructions executed in U-pipe.
• MMX instructions executed in V-pipe (101011/1):
  -- Total number of MMX instructions executed in V-pipe.
• EMMS instructions executed (101101/0):
  -- Counts number of EMMS instructions executed.
• Transition between MMX instructions and FP instructions (101101/1):
  -- Counts first floating-point instruction following any MMX instruction or first MMX instruction following a floating-point instruction. May be used to estimate the penalty in transitions between FP state and MMX state. An even count indicates the processor is in MMX state. An odd count indicates it is in FP state.
• Writes to non-cacheable memory (101110/1):
  -- Counts the number of write accesses to non-cacheable memory. It includes write cycles caused by TLB misses and I/O write cycles. Cycles restarted due to BOFF# are not re-counted.
• Saturating MMX instructions executed (101111/0):
  -- Counts saturating MMX instructions executed, independently of whether or not they actually saturated. Saturating MMX instructions may perform add, subtract, or pack operations .
• Saturations performed (101111/1):
  -- Counts number of MMX instructions that used saturating arithmetic where at least one of the results actually saturated (that is, if an MMX instruction operating on four dwords saturated in three out of the four results, the counter will be incremented by only one).
• Number of cycles not in HALT (HLT) state (110000/0):
  -- This event counts the number of cycles the processor is not idle due to HALT (HLT) instruction. This event will enable the user to calculate "net CPI". Note that during the time that the processor is executing the HLT instruction, the Time Stamp Counter (TSC) is not disabled. Since this event is controlled by the Counter Controls CC0, CC1 it can be used to calculate the CPI at CPL=3 which the TSC cannot provide.
• MMX instruction data reads (110001/0):
  -- Analogous to "Data reads", counting only MMX instruction accesses.
• MMX instruction data read misses (110001/1):
  -- Analogous to "Data read misses", counting only MMX instruction accesses.
• Floating-Point stalls (110010/0):
  -- This event counts the number of clocks while pipe is stalled due to a floating-point freeze.
• Number of Taken Branches (110010/1):
  -- This event counts the number of taken branches.
• D1 starvation and FIFO is empty (110011/0), D1 starvation and only one instruction in FIFO (110011/1):
  -- The D1 stage can issue 0, 1, or 2 instructions per clock if instructions are available in the FIFO buffer. The first event counts how many times D1 cannot issue ANY instructions because the FIFO buffer is empty. The second event counts how many times the D1-stage issues just a single instruction because the FIFO buffer had just one instruction ready. Combined with two other events, Instruction Executed (010110) and Instruction Executed in the V-pipe (010110), the second event enables the user to calculate the number of times pairing rules prevented issue of two instructions.
• MMX instruction data writes (110001/1):
  -- Analogous to "Data writes", counting only MMX instruction accesses.
• MMX instruction data write misses (110100/1):
  -- Analogous to "Data write misses", counting only MMX instruction accesses.
• Pipeline flushes due to wrong branch prediction (110101/0), Pipeline flushes due to wrong branch prediction resolved in WB-stage(110101/1):
  -- Counts any pipeline flush due to a branch which the pipeline did not follow correctly. It includes cases where a branch was not in the BTB, cases where a branch was in the BTB but was mispredicted, and cases where a branch was correctly predicted but to the wrong address. Branches are resolved in either the Execute stage (E-stage) or the Writeback stage (WB-stage). In the latter case, the misprediction penalty is larger by one clock. The first event listed above counts the number of incorrectly predicted branches resolved in either the E-stage or the WB-stage. The second event counts the number of incorrectly predicted branches resolved in the WB-stage. The difference between these two counts is the number of E-stage resolved branches.
• Misaligned data memory reference on MMX instruction (110110/0):
  -- Analogous to "Misaligned data memory reference", counting only MMX instruction accesses.
• Pipeline stalled waiting for data memory read ( 110110/1):
  -- Analogous to "Pipeline stalled waiting for data memory read", counting only MMX technology accesses.
• Returns predicted incorrectly or not predicted at all (110111/0):
  -- These are the actual number of Returns that were either incorrectly predicted or were not predicted at all. It is the difference between the total number of executed returns and the number of returns that were correctly predicted. Only RET instructions are counted (that is, IRET instructions are not counted).
• Returns predicted (correctly and incorrectly) (110111/1):
  -- This is the actual number of Returns for which a prediction was made. Only RET instructions are counted (that is, IRET instructions are not counted).
• MMX technology multiply unit interlock (111000/0):
  -- This event counts the number of clocks the pipe is stalled because the destination of a previous MMX technology multiply instruction is not yet ready. The counter will not be incremented if there is another cause for a stall. For each occurrence of a multiply interlock, this event may be counted twice (if the stalled instruction comes on the next clock after the multiply) or only once (if the stalled instruction comes two clocks after the multiply).
• MOVD/MOVQ store stall due to previous operation (111000/1):
  -- Number of clocks a MOVD/MOVQ store is stalled in D2 stage due to a previous MMX technology operation with a destination to be used in the store instruction.
• Returns (111001/0):
  -- This is the actual number of Returns executed. Only RET instructions are counted (that is, IRET instructions are not counted). Any exception taken on a RET instruction also updates this counter.
• RSB overflows (111001/1):
  -- This event counts the number of times the Return Stack Buffer (RSB) cannot accommodate a call address.
• BTB false entries (111010/0):
  -- This event counts the number of false entries in the Branch Target Buffer. False entries are causes for misprediction other than a wrong prediction.
• BTB miss-prediction on a Not-Taken Branch (111010/1):
  -- This event counts the number of times the BTB predicted a Not-Taken branch as Taken.
• Number of clocks stalled due to full write buffers while executing MMX instructions (111011/0):
  -- Analogous to "Number of clocks stalled due to full write buffers", counting only MMX instruction accesses.
• Stall on MMX instruction write to an E or M state line (111011/1):
  -- Analogous to "Stall on write to an E or M state line", counting only MMX instruction accesses.
  

6.2 Dynamic Execution (P6-Family) Performance Monitoring Events

This section describes the counters on P6-family processors. Table 4-2 lists the events that can be counted with the performance-monitoring counters and read with the RDPMC instruction.

In the table, the:

• Unit column gives the microarchitecture or bus unit that produces the event.
• Event number column gives the hexadecimal number identifying the event.
• Mnemonic event name column gives the name of the event.
• Unit mask column gives the unit mask required (if any).
• Description column describes the event.
• Comments column gives additional information about the event.

These performance monitoring events are intended to be used as guides for performance tuning. The counter values reported are not guaranteed to be absolutely accurate and should be used as a relative guide for tuning. Known discrepancies are documented where applicable. All performance events are model-specific to P6-family processors and are not architecturally guaranteed in future versions of the processor. All performance event encodings not listed in the table are reserved and their use will result in undefined counter results.

Further details will be made available in a later version of this document.

See the end of the table for notes related to certain entries in the table.