(#8394) Intel 486 DX2 Processor SmartDie Product Specification

1.0 Die Specifications

NOTE: The plot and the die photo on the opposite page indicate the orientation of the die in the GEL-PAK* (shipping container). Die are aligned as shown relative to a 45° notch which is in one corner of the GEL-PAK. An Intel Internal manufacturing name "80G4C" appears on 80486 DX2 3.3V die.

1.1 Pad Description

Notes:

I. N.C. signifies no connect These pads must not be connected.
2. The symbol "#" is used at the end of the signal name to denote an active low signal.
3. X-Y pad coordinates represents bond pad centers and are relative to the center of the die.

Boundary Scan (JTAG} is implemented through the following pads: 155 (TMS), 154 (TDI) 90 (TCK), 25 (TDO).

Intel has instituted full-speed functional testing at the die level for all SmartDie^TM products. This level of testing is ordinarily performed only after assembly into a package. Each die is tested to the same electrical limits as the equivalent packaged unit.

Wafer Probe

Wafer probing is performed on every wafer produced in Intel Fabs. The process consists of specific electrical tests and device-specific functionality tests.

At the wafer level. built-in test structures are probed to verify that device electrical characteristics are in control and meet specifications. Measurements are made of transistor threshold voltages and current characteristics; poly and contact resistance; gate oxide and junction integrity: and specific parameters critical to the particular technology and device type. Wafer-to-wafer, across-the-wafer run-to-run variation and conformance to spec limits are checked.

The actual devices on each wafer are then probed for both functionality and performance to specifications Additional reliability tests are also included in the probe steps.

Wafer Saw

Probed wafers are transferred to Intel's assembly sites to be sawed. The saw cuts totally through the wafer.

Die Inspection

Upon completion of the wafer saw, the die are moved to pick and place equipment that removes reject die. The remaining die are submitted to the same visual inspection as standard packaged product. The compliant die are then transferred to GEL PAKs for shipment.

Packing Procedure

Intel will ship all Intel die products in GEL-PAKs GEL-PAKs eliminate the die edge damage usually associated with die cavity plates or chip trays.

The backside of each die adheres to the gel membrane in the GEL-PAK eliminating the risk of damage to the active die surface. A simple vacuum release mechanism allows for pick and place removal at the customer's site.

Only die from the same wafer lot are packaged together in a GEL-PAK, and all die are placed in the GEL-PAKs with a consistent orientation. The GEL-PAKs are then sealed and labeled with the following information:

• Intel SmartDie
• Intel Part Number
• Spec
• Customer Part Number (if applicable)
• Fab Lot Number
• Quantity
• Assembly Lot Traveler Number
• Seal Date
• ROM Code (if applicable)

Inspection Steps

Multiple inspection steps are performed during the die fabrication and packing flow. These steps are performed according to the same specifications and criteria established for Intel's standard packaged product. Specific inspection steps include a wafer saw visual as well as a final die visual just before die are sealed in moisture barrier bags.

Storage Requirements

Intel die products will be shipped in GEL-PAKs and sealed in a moisture-barrier anti-static bag with a desiccant. No special storage procedures are re quired while the bag is still unopened. Once opened, the GEL-PAK should be stored in a dry. inert atmosphere to prevent corrosion of the bond pads.

ESD

Components are ESD sensitive.

3.0 Specifications

Specifications within this document are specific to a particular die revision and are subject to change without notice. Verify with your local Intel Sales Office that you have the latest data before finalizing a design.

3.1 Physical Specifications

Substrate Bias Condition: V_SS

Post-Saw Die Dimensions:
Mils; X = 451 i 0.5. Y = 261 I 0.5
See associated Die/Bond Pad Layout for X Y orientation.

Die Backside Material: (outer most layer first)

1500 (t) 500 Angstroms Gold, 200 (t) 100 Angstroms Chrome

Mils; 4.6 x 4.6 (single pads),
Microns: 118 x 118 (single pads)

3.2 DC Specifications

Absolute Maximum Ratings*
GEL-PAK Storage Temperature 0°C to + 70°C
Junction Temperature under Bias -65°C to + 110.0°C
Supply Voltage with Respect to V_SS -0.5V to + 6.5V
Voltage on Other Pads - 0.5V to V_CC + 0.5V

Operating Conditions*
Digital Supply Voltage (V_CC) 3.3V + 0.3V
Junction Temperature under Bias (TJ) 0°C to 80°C
Core Operating Frequency 40/50 MHz

Minimum Pad Pitch;
Pads may not be evenly pitched. Minimum pitch is 142.5 microns (5.6 mils).

Bond Pad Metalization (outermost layer first)
1-Micron Aluminum (0.5% Copper). 0.1 Microns Titanium

Die Revision: aC-0

Pads per Die: 236

Intel Fabrication Process: CHMOS V (min. feature size 0.8 microns)

Passivation: (outermost layer first)

Notice: This document contains preliminary in formation on new products in production It is valid for the devices indicated in the revision history. This specification is subject to change without no tice. Verify with your local Intel sales office that you have the latest SmartDie Product Specification before finalizing a design

• Warning: Stressing the device beyond the "Absolute Maximum Ratings" may cause permanent damage. These are stress ratings only. Operation beyond the "Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions" may affect device ability.

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