************** IBIS I/0 BUFFER MODEL RELEASE NOTES ********************* COPYRIGHT 1995 BY INTEL CORP. Dear Customer: Enclosed are the latest Pentium(R) Pro Processor I/O buffer models. These models are IBIS 2.1 compliant. The IBIS (I/O Buffer Information Specification) format is an industry standard format used for exchanging I/O buffer information and is supported by most major CAE vendors. There are two specific features of IBIS version 2.1 that your simulator must support. The GTL+ drivers use a "controlled rise time" feature that makes the output switching waveform significantly non-linear. To obtain accurate results using the GTL+ models your simulator MUST support the [Rising waveform] and [Falling waveform] keywords in the IBIS file (i.e. must support a "controlled rise time" or "graduated turn on" style buffer). Note that the data in the waveform tables (a voltage vs. time curve along with the loading information) can be used as a golden waveform to verify your simulator's results. If you are unsure if your simulator supports these features contact your simulator vendor. For more information on IBIS models in general, contact the IBIS Open forum at ibis-request@vhdl.org. CONTENTS: A short directory of the files contained in this release follows: File Description ---- ----------- pentpro.ibs IBIS file for the Pentium(R) Pro processor pentpro.pak Pentium Pro processor package stub modeling information readme.txt This readme NOTE: Contact your Intel representative for the most current information on 82450 PCIset I/O buffer models. TIME TO MEASUREMENT VOLTAGE: The IBIS files contain the information required to perform a "time to measurement voltage" simulation. Time to measurement voltage is the time from when the output starts switching to when it crosses a specific voltage level. This parameter is measured under the same loading conditions as the device's Tco or Tpd parameter and is required by most simulators in order to do board level timing calculations. This parameter is also used to determine the placement of the receiver setup and hold windows for signal quality analysis. The [Model] keyword subparameter "Vmeas" lists the measurement voltage while the subparameters Cref, Rref and Vref specify the loading conditions. There is no parameter specifying a direct time to measurement voltage, as this is simulator dependent. C_COMP MIN and MAX VALUE: IBIS models of an I/O buffer include a parameter called C_comp; C_comp represents the input or output capacitance of a receiver or driver. In accordance with the IBIS specification, the numerically largest value of C_comp is listed as the MAX value while the numerically smallest value of C_comp is listed as the MIN value. However, be aware that when building a fast corner model (fastest edge rate /strongest drive I/O buffer model) from the IBIS data some simulator vendor's translation software will use the MAX value of C_comp instead of the more appropriate MIN value. Likewise, when building a slow corner model the MIN value of C_comp may be used instead of the MAX value. If this is the case you will have to edit the resultant models so that the proper value of C_comp is used. PACKAGE STUB MODELING: Intel has determined that, to properly model the effects of the "package stub" (connection between the die pad and the external pin), the package traces and pins should be represented using one or more transmission line segments. The IBIS standard does not yet currently support this style of package modeling. Therefore, the lumped inductance/capacitance/resistance package parameters in the IBIS files SHOULD NOT be used. Instead, a separate package file has been included with this release. The file "pentpro.pak" contains information for the Pentium Pro processor. For packaging information relating to the 82450 PCIset components, please contact your Intel representative. NOTE: For the recommended minimum and maximum impedance values for simulation purposes, refer to the "Pentium(R)Pro Processor GTL+ Layout Guidelines" document available from Intel (order number 242765-001). The transmission line package models must be inserted between the output of the buffer and the net it is driving. Likewise, the package model must also be placed between a net and the input of a receiver model. This is generally done by editing your simulator's net description or topology file. GTL+ SIMULATION CONDITIONS: IMPORTANT: Refer to the "Pentium(R)Pro Processor GTL+ Layout Guidelines" document for specific and detailed information on GTL+ bus simulations and analysis of simulation results. Tco Measurement Conditions -- Pentium(R) Pro Processor ----------------------------------------------------------------------- Tco (clock to output delay) for GTL+ signals are measured from the clock input crossing 1.5v to when the GTL+ output signal crosses 1.0v as it drives a 25 ohm load terminated at 1.5v. Tco numbers are valid at the pin (i.e., the Tco specification includes the delay between the pad of the silicon and the external pin of the device) and assumes a .9 in package stub. Please note that the Tco number does NOT include the delay thru the socket. Pentium Pro Processor CMOS signal timings are measured from input clock crossing 1.5v to the output crossing 1.5v when driving a 150 ohm resistor terminated to 3.3v. As with the GTL+ timing, Tco is valid at the pin. To account for changes in device propagation delay due to the differences between the data book load and the actual loading conditions, do the following: Perform a simulation in which the driver is driving a single 25 ohm resistor connected to 1.5v thru a .9 in package stub. Record the time from which the output starts switching to when the output waveform crosses 1v at the device pin. Next, perform a simulation into your actual network and again note the time it took the output to go from quiescent to the 1v mark. The difference between the two numbers is the difference in device propagation delay due to the changing output load and must be accounted for in your timing budget. Propagation delay differences due to load for the Pentium Pro Processor CMOS signals are determined as above, substituting the proper loading network (150 ohms to 3.3v). VALIDATION LEVEL AND MODEL LIMITS: The Pentium Pro Processor model is based on silicon simulation and has been validated by silicon measurements. The models represent the expected I/O buffer strength and edge rate variation over the specified temperature, process and voltage limits. The Pentium Pro Processor "MAX" data represents a single buffer switching in isolation while the "MIN" data represents a buffer under multiple outputs switching conditions. Please note that in all cases, the Tco numbers listed in the data sheets are guaranteed over multiple outputs switching.