-- ****************************** -- Copyright Intel Corporation -- ********************************************************************* -- Intel Corporation makes no warranty for the use of its products -- and assumes no responsibility for any errors which may appear in -- this document nor does it make a commitment to update the information -- contained herein. -- ********************************************************************* -- -- ********************************************************************* -- Boundary-Scan Description language (BSDL version 0.0) is a de-facto -- standard means of describing essential features of ANSI/IEEE 1149.1-1990 -- compliant devices. This language is under consideration by the IEEE for -- formal inclusion within a supplement to the 1149.1-1990 standard. The -- generation of the supplement entails an extensive IEEE review and a formal -- acceptance balloting procedure which may change the resultant form of the -- language. Be aware that this process may extend well into 1994, and at -- this time the IEEE does not endorse or hold an opinion on the language. -- ********************************************************************* -- -- -- Intel Pentium(R) Pro Processor BSDL File -- B0, C0, sA0, and sA1 steppings -- ------------------------------------------- -- entity P6_0 is -- -- Generic description -- generic(PHYSICAL_PIN_MAP: string := "PGA_P6"); -- -- Pentium Pro Processor Port Definitions -- port(A20M : in bit; A : inout bit_vector(35 downto 3); -- Address bus ADS : inout bit; AERR : inout bit; AP : inout bit_vector(0 to 1); BCLK : in bit; BERR : inout bit; BINIT : inout bit; BNR : inout bit; BPM : inout bit_vector(3 downto 0); BPRI : in bit; BR : in bit_vector(0 to 3); D : inout bit_vector(63 downto 0); DBSY : inout bit; DEFER : in bit; DEP : inout bit_vector(0 to 7); DRDY : inout bit; FERR : out bit; FLUSH : in bit; FRCERR : inout bit; HIT : inout bit; HITM : inout bit; IERR : out bit; IGNNE : in bit; INIT : in bit; LINT0INT : in bit; LINT1NMI : in bit; LOCK : inout bit; PICD : inout bit_vector(1 downto 0); PICCLK : in bit; PREQ : in bit; PRDY : out bit; PWRGOOD : in bit; REQ : inout bit_vector(4 downto 0); RESET : in bit; RP : inout bit; RS : in bit_vector(0 to 2); RSMI : in bit; RSP : in bit; STPCLK : in bit; TCK : in bit; TDI : in bit; TDO : out bit; THERMTRIP : out bit; TMS : in bit; TRDY : in bit; TRST : in bit; EMI : linkage bit_vector(1 to 4); -- EMI at GND LEVEL NC : linkage bit_vector(1 to 34); -- NO CONNECTS PLL : linkage bit_vector(1 to 2); -- PLL decoupling VCCP : linkage bit_vector(1 to 47); -- Primary VCC 2.9V VCCS : linkage bit_vector(1 to 28); -- Secondary VCC 3.3V VREF : linkage bit_vector(0 to 7); -- GTL reference voltage VSS : linkage bit_vector(1 to 101) -- GND or VSS ); -- -- Use section -- use STD_1149_1_1990.all; use p6_04.all; -- -- Pentium Pro Processor Physical Pin Map -- attribute PIN_MAP of P6_0 : entity is PHYSICAL_PIN_MAP; constant PGA_P6 : PIN_MAP_STRING := "A20M : A11," & "A : (C1, E9, E7, E5, G9, E3, E1, J9, G5, G7, L9, G3, J7, G1, " & " J3, J5, J1, L7, N9, L3, L5, N3, N7, N1, N5, Q9, Q1, Q7, " & " Q3, S1, Q5, S3, S5), " & "ADS : AE3," & "AERR : AE9," & "AP : (U1, S9)," & "BCLK : A19," & "BERR : C5," & "BINIT : AC43," & "BNR : U7," & "BPM : (AC39, AE43, AA39, AC41)," & "BPRI : U5," & "BR : (AC5, W3, AA1, U9)," & "D : (W43, Y47, W45, U43, S39, W47, S41, U45, U47, S43, S45, " & " Q41, Q39, S47, Q43, Q45, N43, Q47, N41, N39, L43, N45, " & " N47, L41, L47, J43, L39, L45, J41, J47, J45, J39, G47, " & " G43, G41, G45, G39, E47, E43, E45, E41, E39, C47, C41, " & " C45, C43, C39, A45, C37, A37, A43, C35, A41, A39, A35, " & " A33, C33, C31, A31, C29, A29, C27, A27, C25), " & "DBSY : AA5, " & "DEFER : Y5, " & "DEP : (AC45, Y43, W39, AC47, W41, AA47, Y45, U39), " & "DRDY : AA3, " & "FERR : C17, " & "FLUSH : A15, " & "FRCERR : C9, " & "HIT : AC3, " & "HITM : AA7, " & "IERR : C3, " & "IGNNE : A9, " & "INIT : C11, " & "LINT0INT : AG43, " & "LINT1NMI : AG41, " & "LOCK : AA9, " & "PICD : (AE41, AA41), " & "PICCLK : AA43, " & "PLL : (C19, C23), " & "PREQ : AA45, " & "PRDY : Y39, " & "PWRGOOD : AG7, " & "REQ : (W5, Y1, Y3, W7, W9), " & "RESET : Y41, " & "RP : AC7, " & "RS : (AC9, AE5, AE7), " & "RSMI : W1, " & "RSP : U3, " & "STPCLK : A3, " & "TCK : A5, " & "TDI : A13, " & "TDO : C13, " & "THERMTRIP : A17, " & "TMS : C15, " & "TRDY : Y9, " & "TRST : A7, " & "EMI : (B2, B46, BC1, BC47), " & "NC : (A21, AC1, AE1, AE45, AG1, AG3, AG5, AG9, AG39, AG47, " & " AS1, AS3, AS5, AS7, AS9, AS39, AS41, AS43, AS45, AS47, BA11, " & " BA13, BA15, BA33, BA35, BA37, BC11, BC13, BC15, BC33, " & " BC35, BC37, C21, L1), " & "VCCP : (B4, B8, B16, B24, B32, B40, B44, F2, F6, F42, F46, K4, K44, " & " P2, P6, P42, P46, T4, T44, X6, X42, AB4, AB44, AJ3, AJ7, " & " AJ41, AJ45, AL1, AL5, AL9, AL39, AL43, AL47, AN3, AN7, AN41, " & " AN45, AQ1, AQ5, AQ9, AQ39, AQ43, AQ47, BA17, BA21, BA25, " & " BA29), " & "VCCS : (AU1, AU5, AU9, AU39, AU43, AU47, AW3, AW7, AW41, AW45, AY1, " & " AY3, AY5, AY7, AY9, AY39, AY41, AY43, AY45, AY47, BA3, BA7, " & " BA41, BA45, BC19, BC23, BC27, BC31), " & "VREF : (A1, C7, S7, Y7, A47, AE47, U41, AG45)," & "VSS : (A23, A25, B6, B12, B20, B28, B36, B42, F4, F8, F40, " & " F44, K2, K6, K8, K40, K42, K46, P4, P8, P40, P44, T2, T6, " & " T8, T40, T42, T46, X2, X4, X8, X40, X44, X46, AB2, AB6, AB8, " & " AB40, AB42, AB46, AE39, AF2, AF4, AF6, AF8, AF40, AF42, AF44," & " AF46, AJ1, AJ5, AJ9, AJ39, AJ43, AJ47, AL3, AL7, AL41, AL45, " & " AN1, AN5, AN9, AN39, AN43, AN47, AQ3, AQ7, AQ41, AQ45, AU3, " & " AU7, AU41, AU45, AW1, AW5, AW9, AW39, AW43, AW47, BA1, BA5, " & " BA9, BA19, BA23, BA27, BA31, BA39, BA43, BA47, BC3, BC5, " & " BC7, BC9, BC17, BC21, BC25, BC29, BC39, BC41, BC43, BC45)"; -- -- Scan Port Identification -- attribute TAP_SCAN_IN of TDI :signal is true; attribute TAP_SCAN_MODE of TMS :signal is true; attribute TAP_SCAN_OUT of TDO :signal is true; attribute TAP_SCAN_RESET of TRST :signal is true; attribute TAP_SCAN_CLOCK of TCK :signal is (2.5e7, both); -- -- Instruction Register and Op-codes -- attribute Instruction_Length of P6_0: entity is 6; attribute Instruction_Opcode of P6_0: entity is "EXTEST (000000), " & "SAMPLE (000001), " & "IDCODE (000010), " & "CLAMP (000100), " & -- "RUNBIST (000111), " & "HIGHZ (001000), " & "BYPASS (111111), " & "Reserved ( 000011, 000101, 000110, " & " 001001, 001010, 001011, 001100, 001101, 001110, 001111, " & " 010000, 010001, 010010, 010011, 010100, 010101, 010110, 010111, " & " 011000, 011001, 011010, 011011, 011100, 011101, 011110, 011111, " & " 100000, 100001, 100010, 100011, 100100, 100101, 100110, 100111, " & " 101000, 101001, 101010, 101011, 101100, 101101, 101110, 101111, " & " 110000, 110001, 110010, 110011, 110100, 110101, 110110, 110111, " & " 111000, 111001, 111010, 111011, 111100, 111101, 111110 ) "; attribute Instruction_Capture of P6_0: entity is "000001"; attribute Instruction_Disable of P6_0: entity is "HIGHZ"; attribute Instruction_Private of P6_0: entity is "Reserved"; -- -- Pentium Pro Processor IDCODE Register -- attribute Idcode_Register of P6_0: entity is "0001" & -- Version, B0, C0, sA0, or sA1 steppings "1000001011000001" & -- Part number "00000001001" & -- Manufacturer's identity "1"; -- Required by the 1149.1 standard -- -- Pentium Pro Processor Data Register Access -- attribute Register_Access of P6_0: entity is "BOUNDARY (EXTEST, SAMPLE), " & -- "RUNBIST[1] (RUNBIST), " & "IDCODE (IDCODE), " & "BYPASS (CLAMP, HIGHZ, BYPASS)"; -- -- Pentium Pro Processor Boundary Register Description -- -- Cell 0 is closest to TDO -- -- BS_4 : INPUT -- BC_2 : OUTPUT2 -- BS_G : GTL BIDIR/CONTROL Combo cell -- attribute BOUNDARY_CELLS of P6_0: entity is "BC_2, BS_4, BS_G"; attribute BOUNDARY_LENGTH of P6_0: entity is 160; attribute BOUNDARY_REGISTER of P6_0: entity is -- num cell port function safe [ccell disval rslt] " 159 (BS_4, BCLK, clock, X ), " & " 158 (BS_4, PWRGOOD, input, 1 ), " & " 157 (BC_2, *, internal, 1 ), " & " 156 (BC_2, THERMTRIP, output2, X ), " & " 155 (BS_4, STPCLK, input, X ), " & " 154 (BS_4, A20M, input, X ), " & " 153 (BS_4, FLUSH, input, X ), " & " 152 (BS_4, INIT, input, X ), " & " 151 (BS_4, IGNNE, input, X ), " & " 150 (BC_2, FERR, output2, X ), " & " 149 (BS_G, FRCERR, output2, 1, 149, 1, Weak1 ), " & " 149 (BS_G, FRCERR, input, 1 ), " & " 148 (BS_G, BERR, output2, 1, 148, 1, Weak1 ), " & " 148 (BS_G, BERR, input, 1 ), " & " 147 (BC_2, IERR, output2, X ), " & " 146 (BS_G, A(35), output2, 1, 146, 1, Weak1 ), " & " 146 (BS_G, A(35), input, 1 ), " & " 145 (BS_G, A(34), output2, 1, 145, 1, Weak1 ), " & " 145 (BS_G, A(34), input, 1 ), " & " 144 (BS_G, A(33), output2, 1, 144, 1, Weak1 ), " & " 144 (BS_G, A(33), input, 1 ), " & " 143 (BS_G, A(32), output2, 1, 143, 1, Weak1 ), " & " 143 (BS_G, A(32), input, 1 ), " & " 142 (BS_G, A(31), output2, 1, 142, 1, Weak1 ), " & " 142 (BS_G, A(31), input, 1 ), " & " 141 (BS_G, A(30), output2, 1, 141, 1, Weak1 ), " & " 141 (BS_G, A(30), input, 1 ), " & " 140 (BS_G, A(29), output2, 1, 140, 1, Weak1 ), " & " 140 (BS_G, A(29), input, 1 ), " & " 139 (BS_G, A(28), output2, 1, 139, 1, Weak1 ), " & " 139 (BS_G, A(28), input, 1 ), " & " 138 (BS_G, A(27), output2, 1, 138, 1, Weak1 ), " & " 138 (BS_G, A(27), input, 1 ), " & " 137 (BS_G, A(26), output2, 1, 137, 1, Weak1 ), " & " 137 (BS_G, A(26), input, 1 ), " & " 136 (BS_G, A(25), output2, 1, 136, 1, Weak1 ), " & " 136 (BS_G, A(25), input, 1 ), " & " 135 (BS_G, A(24), output2, 1, 135, 1, Weak1 ), " & " 135 (BS_G, A(24), input, 1 ), " & " 134 (BS_G, A(23), output2, 1, 134, 1, Weak1 ), " & " 134 (BS_G, A(23), input, 1 ), " & " 133 (BS_G, A(22), output2, 1, 133, 1, Weak1 ), " & " 133 (BS_G, A(22), input, 1 ), " & " 132 (BS_G, A(21), output2, 1, 132, 1, Weak1 ), " & " 132 (BS_G, A(21), input, 1 ), " & " 131 (BS_G, A(20), output2, 1, 131, 1, Weak1 ), " & " 131 (BS_G, A(20), input, 1 ), " & " 130 (BS_G, A(19), output2, 1, 131, 1, Weak1 ), " & " 130 (BS_G, A(19), input, 1 ), " & " 129 (BS_G, A(18), output2, 1, 129, 1, Weak1 ), " & " 129 (BS_G, A(18), input, 1 ), " & " 128 (BS_G, A(17), output2, 1, 128, 1, Weak1 ), " & " 128 (BS_G, A(17), input, 1 ), " & " 127 (BS_G, A(16), output2, 1, 127, 1, Weak1 ), " & " 127 (BS_G, A(16), input, 1 ), " & " 126 (BS_G, A(15), output2, 1, 126, 1, Weak1 ), " & " 126 (BS_G, A(15), input, 1 ), " & " 125 (BS_G, A(14), output2, 1, 125, 1, Weak1 ), " & " 125 (BS_G, A(14), input, 1 ), " & " 124 (BS_G, A(13), output2, 1, 124, 1, Weak1 ), " & " 124 (BS_G, A(13), input, 1 ), " & " 123 (BS_G, A(12), output2, 1, 123, 1, Weak1 ), " & " 123 (BS_G, A(12), input, 1 ), " & " 122 (BS_G, A(11), output2, 1, 122, 1, Weak1 ), " & " 122 (BS_G, A(11), input, 1 ), " & " 121 (BS_G, A(10), output2, 1, 121, 1, Weak1 ), " & " 121 (BS_G, A(10), input, 1 ), " & " 120 (BS_G, A(9), output2, 1, 120, 1, Weak1 ), " & " 120 (BS_G, A(9), input, 1 ), " & " 119 (BS_G, A(8), output2, 1, 119, 1, Weak1 ), " & " 119 (BS_G, A(8), input, 1 ), " & " 118 (BS_G, A(7), output2, 1, 118, 1, Weak1 ), " & " 118 (BS_G, A(7), input, 1 ), " & " 117 (BS_G, A(6), output2, 1, 117, 1, Weak1 ), " & " 117 (BS_G, A(6), input, 1 ), " & " 116 (BS_G, A(5), output2, 1, 116, 1, Weak1 ), " & " 116 (BS_G, A(5), input, 1 ), " & " 115 (BS_G, A(4), output2, 1, 115, 1, Weak1 ), " & " 115 (BS_G, A(4), input, 1 ), " & " 114 (BS_G, A(3), output2, 1, 114, 1, Weak1 ), " & " 114 (BS_G, A(3), input, 1 ), " & " 113 (BS_G, AP(0), output2, 1, 113, 1, Weak1 ), " & " 113 (BS_G, AP(0), input, 1 ), " & " 112 (BS_G, AP(1), output2, 1, 112, 1, Weak1 ), " & " 112 (BS_G, AP(1), input, 1 ), " & " 111 (BS_4, RSP, input, X ), " & " 110 (BS_4, RSMI, input, X ), " & " 109 (BS_4, BPRI, input, X ), " & " 108 (BS_G, BNR, output2, 1, 108, 1, Weak1 ), " & " 108 (BS_G, BNR, input, 1 ), " & " 107 (BS_4, BR(1), input, X ), " & " 106 (BS_4, BR(2), input, X ), " & " 105 (BS_4, BR(3), input, X ), " & " 104 (BS_G, REQ(4), output2, 1, 104, 1, Weak1 ), " & " 104 (BS_G, REQ(4), input, 1 ), " & " 103 (BS_G, REQ(3), output2, 1, 103, 1, Weak1 ), " & " 103 (BS_G, REQ(3), input, 1 ), " & " 102 (BS_G, REQ(2), output2, 1, 102, 1, Weak1 ), " & " 102 (BS_G, REQ(2), input, 1 ), " & " 101 (BS_G, REQ(1), output2, 1, 101, 1, Weak1 ), " & " 101 (BS_G, REQ(1), input, 1 ), " & " 100 (BS_G, REQ(0), output2, 1, 100, 1, Weak1 ), " & " 100 (BS_G, REQ(0), input, 1 ), " & " 99 (BS_4, DEFER, input, X ), " & " 98 (BS_G, DRDY, output2, 1, 98, 1, Weak1 ), " & " 98 (BS_G, DRDY, input, 1 ), " & " 97 (BS_4, TRDY, input, X ), " & " 96 (BS_G, DBSY, output2, 1, 96, 1, Weak1 ), " & " 96 (BS_G, DBSY, input, 1 ), " & " 95 (BS_G, HIT, output2, 1, 95, 1, Weak1 ), " & " 95 (BS_G, HIT, input, 1 ), " & " 94 (BS_G, HITM, output2, 1, 94, 1, Weak1 ), " & " 94 (BS_G, HITM, input, 1 ), " & " 93 (BS_G, RP, output2, 1, 93, 1, Weak1 ), " & " 93 (BS_G, RP, input, 1 ), " & " 92 (BS_4, BR(0), input, X ), " & " 91 (BS_G, ADS, output2, 1, 91, 1, Weak1 ), " & " 91 (BS_G, ADS, input, 1 ), " & " 90 (BS_G, LOCK, output2, 1, 90, 1, Weak1 ), " & " 90 (BS_G, LOCK, input, 1 ), " & " 89 (BS_4, RS(0), input, X ), " & " 88 (BS_4, RS(1), input, X ), " & " 87 (BS_4, RS(2), input, X ), " & " 86 (BS_G, AERR, output2, 1, 86, 1, Weak1 ), " & " 86 (BS_G, AERR, input, 1 ), " & " 85 (BS_4, LINT1NMI, input, X ), " & " 84 (BS_4, LINT0INT, input, X ), " & " 83 (BS_G, PICD(1), output2, 1, 83, 1, Weak1 ), " & " 83 (BS_G, PICD(1), input, 1 ), " & " 82 (BS_G, PICD(0), output2, 1, 82, 1, Weak1 ), " & " 82 (BS_G, PICD(0), input, 1 ), " & " 81 (BS_4, PICCLK, clock, X ), " & " 80 (BS_G, BPM(3), output2, 1, 80, 1, Weak1 ), " & " 80 (BS_G, BPM(3), input, 1 ), " & " 79 (BS_G, BPM(2), output2, 1, 79, 1, Weak1 ), " & " 79 (BS_G, BPM(2), input, 1 ), " & " 78 (BS_G, BPM(1), output2, 1, 78, 1, Weak1 ), " & " 78 (BS_G, BPM(1), input, 1 ), " & " 77 (BS_G, BPM(0), output2, 1, 77, 1, Weak1 ), " & " 77 (BS_G, BPM(0), input, 1 ), " & " 76 (BS_4, PREQ, input, X ), " & " 75 (BC_2, PRDY, output2, 1 ), " & " 74 (BS_4, RESET, input, X ), " & " 73 (BS_G, BINIT, output2, 1, 73, 1, Weak1 ), " & " 73 (BS_G, BINIT, input, 1 ), " & " 72 (BS_G, DEP(0), output2, 1, 72, 1, Weak1 ), " & " 72 (BS_G, DEP(0), input, 1 ), " & " 71 (BS_G, DEP(1), output2, 1, 71, 1, Weak1 ), " & " 71 (BS_G, DEP(1), input, 1 ), " & " 70 (BS_G, DEP(2), output2, 1, 70, 1, Weak1 ), " & " 70 (BS_G, DEP(2), input, 1 ), " & " 69 (BS_G, DEP(3), output2, 1, 69, 1, Weak1 ), " & " 69 (BS_G, DEP(3), input, 1 ), " & " 68 (BS_G, DEP(4), output2, 1, 68, 1, Weak1 ), " & " 68 (BS_G, DEP(4), input, 1 ), " & " 67 (BS_G, DEP(5), output2, 1, 67, 1, Weak1 ), " & " 67 (BS_G, DEP(5), input, 1 ), " & " 66 (BS_G, DEP(6), output2, 1, 66, 1, Weak1 ), " & " 66 (BS_G, DEP(6), input, 1 ), " & " 65 (BS_G, DEP(7), output2, 1, 65, 1, Weak1 ), " & " 65 (BS_G, DEP(7), input, 1 ), " & " 64 (BS_G, D(63), output2, 1, 64, 1, Weak1 ), " & " 64 (BS_G, D(63), input, 1 ), " & " 63 (BS_G, D(62), output2, 1, 63, 1, Weak1 ), " & " 63 (BS_G, D(62), input, 1 ), " & " 62 (BS_G, D(61), output2, 1, 62, 1, Weak1 ), " & " 62 (BS_G, D(61), input, 1 ), " & " 61 (BS_G, D(60), output2, 1, 61, 1, Weak1 ), " & " 61 (BS_G, D(60), input, 1 ), " & " 60 (BS_G, D(59), output2, 1, 60, 1, Weak1 ), " & " 60 (BS_G, D(59), input, 1 ), " & " 59 (BS_G, D(58), output2, 1, 59, 1, Weak1 ), " & " 59 (BS_G, D(58), input, 1 ), " & " 58 (BS_G, D(57), output2, 1, 58, 1, Weak1 ), " & " 58 (BS_G, D(57), input, 1 ), " & " 57 (BS_G, D(56), output2, 1, 57, 1, Weak1 ), " & " 57 (BS_G, D(56), input, 1 ), " & " 56 (BS_G, D(55), output2, 1, 56, 1, Weak1 ), " & " 56 (BS_G, D(55), input, 1 ), " & " 55 (BS_G, D(54), output2, 1, 55, 1, Weak1 ), " & " 55 (BS_G, D(54), input, 1 ), " & " 54 (BS_G, D(53), output2, 1, 54, 1, Weak1 ), " & " 54 (BS_G, D(53), input, 1 ), " & " 53 (BS_G, D(52), output2, 1, 53, 1, Weak1 ), " & " 53 (BS_G, D(52), input, 1 ), " & " 52 (BS_G, D(51), output2, 1, 52, 1, Weak1 ), " & " 52 (BS_G, D(51), input, 1 ), " & " 51 (BS_G, D(50), output2, 1, 51, 1, Weak1 ), " & " 51 (BS_G, D(50), input, 1 ), " & " 50 (BS_G, D(49), output2, 1, 50, 1, Weak1 ), " & " 50 (BS_G, D(49), input, 1 ), " & " 49 (BS_G, D(48), output2, 1, 49, 1, Weak1 ), " & " 49 (BS_G, D(48), input, 1 ), " & " 48 (BS_G, D(47), output2, 1, 48, 1, Weak1 ), " & " 48 (BS_G, D(47), input, 1 ), " & " 47 (BS_G, D(46), output2, 1, 47, 1, Weak1 ), " & " 47 (BS_G, D(46), input, 1 ), " & " 46 (BS_G, D(45), output2, 1, 46, 1, Weak1 ), " & " 46 (BS_G, D(45), input, 1 ), " & " 45 (BS_G, D(44), output2, 1, 45, 1, Weak1 ), " & " 45 (BS_G, D(44), input, 1 ), " & " 44 (BS_G, D(43), output2, 1, 44, 1, Weak1 ), " & " 44 (BS_G, D(43), input, 1 ), " & " 43 (BS_G, D(42), output2, 1, 43, 1, Weak1 ), " & " 43 (BS_G, D(42), input, 1 ), " & " 42 (BS_G, D(41), output2, 1, 42, 1, Weak1 ), " & " 42 (BS_G, D(41), input, 1 ), " & " 41 (BS_G, D(40), output2, 1, 41, 1, Weak1 ), " & " 41 (BS_G, D(40), input, 1 ), " & " 40 (BS_G, D(39), output2, 1, 40, 1, Weak1 ), " & " 40 (BS_G, D(39), input, 1 ), " & " 39 (BS_G, D(38), output2, 1, 39, 1, Weak1 ), " & " 39 (BS_G, D(38), input, 1 ), " & " 38 (BS_G, D(37), output2, 1, 38, 1, Weak1 ), " & " 38 (BS_G, D(37), input, 1 ), " & " 37 (BS_G, D(36), output2, 1, 37, 1, Weak1 ), " & " 37 (BS_G, D(36), input, 1 ), " & " 36 (BS_G, D(35), output2, 1, 36, 1, Weak1 ), " & " 36 (BS_G, D(35), input, 1 ), " & " 35 (BS_G, D(34), output2, 1, 35, 1, Weak1 ), " & " 35 (BS_G, D(34), input, 1 ), " & " 34 (BS_G, D(33), output2, 1, 34, 1, Weak1 ), " & " 34 (BS_G, D(33), input, 1 ), " & " 33 (BS_G, D(32), output2, 1, 33, 1, Weak1 ), " & " 33 (BS_G, D(32), input, 1 ), " & " 32 (BS_G, D(31), output2, 1, 32, 1, Weak1 ), " & " 32 (BS_G, D(31), input, 1 ), " & " 31 (BS_G, D(30), output2, 1, 31, 1, Weak1 ), " & " 31 (BS_G, D(30), input, 1 ), " & " 30 (BS_G, D(29), output2, 1, 30, 1, Weak1 ), " & " 30 (BS_G, D(29), input, 1 ), " & " 29 (BS_G, D(28), output2, 1, 29, 1, Weak1 ), " & " 29 (BS_G, D(28), input, 1 ), " & " 28 (BS_G, D(27), output2, 1, 28, 1, Weak1 ), " & " 28 (BS_G, D(27), input, 1 ), " & " 27 (BS_G, D(26), output2, 1, 27, 1, Weak1 ), " & " 27 (BS_G, D(26), input, 1 ), " & " 26 (BS_G, D(25), output2, 1, 26, 1, Weak1 ), " & " 26 (BS_G, D(25), input, 1 ), " & " 25 (BS_G, D(24), output2, 1, 25, 1, Weak1 ), " & " 25 (BS_G, D(24), input, 1 ), " & " 24 (BS_G, D(23), output2, 1, 24, 1, Weak1 ), " & " 24 (BS_G, D(23), input, 1 ), " & " 23 (BS_G, D(22), output2, 1, 23, 1, Weak1 ), " & " 23 (BS_G, D(22), input, 1 ), " & " 22 (BS_G, D(21), output2, 1, 22, 1, Weak1 ), " & " 22 (BS_G, D(21), input, 1 ), " & " 21 (BS_G, D(20), output2, 1, 21, 1, Weak1 ), " & " 21 (BS_G, D(20), input, 1 ), " & " 20 (BS_G, D(19), output2, 1, 20, 1, Weak1 ), " & " 20 (BS_G, D(19), input, 1 ), " & " 19 (BS_G, D(18), output2, 1, 19, 1, Weak1 ), " & " 19 (BS_G, D(18), input, 1 ), " & " 18 (BS_G, D(17), output2, 1, 18, 1, Weak1 ), " & " 18 (BS_G, D(17), input, 1 ), " & " 17 (BS_G, D(16), output2, 1, 17, 1, Weak1 ), " & " 17 (BS_G, D(16), input, 1 ), " & " 16 (BS_G, D(15), output2, 1, 16, 1, Weak1 ), " & " 16 (BS_G, D(15), input, 1 ), " & " 15 (BS_G, D(14), output2, 1, 15, 1, Weak1 ), " & " 15 (BS_G, D(14), input, 1 ), " & " 14 (BS_G, D(13), output2, 1, 14, 1, Weak1 ), " & " 14 (BS_G, D(13), input, 1 ), " & " 13 (BS_G, D(12), output2, 1, 13, 1, Weak1 ), " & " 13 (BS_G, D(12), input, 1 ), " & " 12 (BS_G, D(11), output2, 1, 12, 1, Weak1 ), " & " 12 (BS_G, D(11), input, 1 ), " & " 11 (BS_G, D(10), output2, 1, 11, 1, Weak1 ), " & " 11 (BS_G, D(10), input, 1 ), " & " 10 (BS_G, D(9), output2, 1, 10, 1, Weak1 ), " & " 10 (BS_G, D(9), input, 1 ), " & " 9 (BS_G, D(8), output2, 1, 9, 1, Weak1 ), " & " 9 (BS_G, D(8), input, 1 ), " & " 8 (BS_G, D(7), output2, 1, 8, 1, Weak1 ), " & " 8 (BS_G, D(7), input, 1 ), " & " 7 (BS_G, D(6), output2, 1, 7, 1, Weak1 ), " & " 7 (BS_G, D(6), input, 1 ), " & " 6 (BS_G, D(5), output2, 1, 6, 1, Weak1 ), " & " 6 (BS_G, D(5), input, 1 ), " & " 5 (BS_G, D(4), output2, 1, 5, 1, Weak1 ), " & " 5 (BS_G, D(4), input, 1 ), " & " 4 (BS_G, D(3), output2, 1, 4, 1, Weak1 ), " & " 4 (BS_G, D(3), input, 1 ), " & " 3 (BS_G, D(2), output2, 1, 3, 1, Weak1 ), " & " 3 (BS_G, D(2), input, 1 ), " & " 2 (BS_G, D(1), output2, 1, 2, 1, Weak1 ), " & " 2 (BS_G, D(1), input, 1 ), " & " 1 (BS_G, D(0), output2, 1, 1, 1, Weak1 ), " & " 1 (BS_G, D(0), input, 1 ), " & " 0 (BS_4, *, internal, 1 ) " ; end P6_0;