Replacing The 82077SL With The 82078 (44PIN)

How to Disable the Native Floppy Controller on the Motherboard
Replacing the 82077SL with a 82078 in a 5.0V Design
Figure 10-3 82077SL Converstion to 82078
Pin Changes on the 44 Pin Part

The BOOTSEL bit allows users to multiplex the output drive signals allowing different drives to be the boot drive. The DSn and MEn bits are considered virtual designations since the DSn and MEn signals get remapped to different corresponding physical FDSn and FDMEn pins, In other words, once the BOOTSEL bit is configured for a non-default selection, all future references made to the controller will be assumed as virtual designations. Note, due to the virtual designations TAPESEL[1:01] = 00 would never enable tape mode due to boot drive restrictions.

10.3 How to Disable the Native Floppy Controller on the Motherboard

There are occasions when the floppy controller designed onto the motherboard of a system needs to be disabled in order to operate another floppy controller on the expansion bus. This can be done without changing the BIOS or remapping the address of the floppy controller (provided there is a jumper, or another way to disable the chipselect on the native controller).

Upon reset the DOR register in the 82078 is set to 00H. If the CS# is left enabled during the POST, the DOR Is set to 0CH, this enables the DMA GATE# bit in the DOR. When this bit is set the 82078 treats a DACK# and a RD# or WR# as an internal chip select (CS#). Bus contention will occur between the native controller and the auxiliary controller if the DMA GATE # bit becomes active, even if the CS # signal is not present.

The proper way to disable the native floppy controller is to disable the CS# before the system is turned on. This will prevent the native controller from getting initialized. Another option is to map the native controller to a secondary address space, then disable the DMA GATE# via the DOR disabling the DMA GATE#. This assumes that the native controller is switched to a secondary address space.

10.4 Replacing the 82077SL with a 82078 In a 5.OV Design

The 82078 easily replaces the 5.OV 820773L with minimum design changes. With a few exceptions, most of the signals are named as they were in the 820773L. Some pins were eliminated and others re named to accommodate a reduced pin count and smaller package.

The connections to the AT bus are the same as the 82077SL with the following exceptions: MFM and IDENT have been removed. The PLL0 pin was re moved. Tape drive mode on the 82078 must be con-figured via the Tape Drive Register (TDR).

The Drive Interface on the 82078 is also similar to the 820775L except as noted: DRVDEN0 and DAVDEN1 on the 82078 take the place of DENSEL, DRATE0, and DRATE1 on the 82077SL. The Drive Specification Command configures the polarity of these pins, thus selecting the density type of the drive. The Motor Enable pins and the Drive Select pins are renamed FDME(0-1) and FDS(O-l) respectively on the 82078. 10K pull-up resistors can be used on the disk interface. See Figure 10-3 for a schematic of the connection.

Figure 10-3. 82077SL Conversion to 82078

Pin Changes on the 44 Pin Part:

If the 44PD EN bit in the powerdown command is set, then the FDS1# and FDMEl# no longer function as drive select and motor enable. Instead these pins become functional as status outputs of PD and IDLE.
INVERT# is removed.
Four NCs (no connects) are removed.
MFM, IDENT have been removed. The 44 pin 82078 only operates in AT/EISA mode.
PLL0 is removed. Hardware configurability for tape drive mode is not supported. Configure tape mode via the TDR register.
DENSEL, DRATEl. DRATE0 pins have been substituted by DRVDEN0, DRVDEN1. The new pins are configured for each drive via the Drive Specification command.
DRV2 and RDGATE are not available.
There are 3 V_SS pins, 2 V_CC pins, one AV_SS and one AV_CC pin.