Replacing The 82077SL WITH 82078 (64PIN)

How to Disable the Native Floppy Controller
Replacing the 82077SL with a 82078 in a 5.0V Design
Pin Chages on the 64 Pin Part

The BOOTSELn bits allow users to multiplex the output drive signals allowing different drives to be the boot drive. The DSn and MEn bits are considered virtual designations since the DSn and MEn signals get remapped to different corresponding physical FDSn and FDMEn pins. In other words, once the BOOTSELn bits are configured for a non-default se lection, all future references made to the controller will be assumed as virtual designations. For exam ple, if BOOTSEL1, BOOTSEL0 = 10 then DOR[1:0] =00 refers to drive 2 and FDS2, FDME2 lines will be activated. Also, if TAPESEL[1:0] = 10, then tape mode is selected whenever FDS0, FDME0 are selected. Note, due to the virtual designations TAPESEL[1:0 ] = 00 would never enable tape mode due to boot drive restrictions.

10.3 How to Disable the Native Floppy Controller on the Motherboard

There are occasions when the floppy controller designed onto the motherboard of a system needs to be disabled in order to operate another floppy con troller on the expansion bus. This can be done without changing the BIOS or remapping the address of the floppy controller (provided there is a Jumper, or another way to disable the chipselect on the native controller).

Upon reset theDOR register in the 82078 is set to 00H. If the CS# is left enabled during the POST, the DOR is set to 0CH, this enables the DMA GATE # bit in the DOR. When this bit is set the 82078 treats a DACK# and a RD# or WR# as an internal chip select (CS#). Bus contention will occur between the native controller and the auxiliary controller if the DMA GATE# bit becomes active, even if the CS # signal is not present.

The proper way to disable the native floppy controller is to disable the CS# before the system is turned on. This will prevent the native controller from get ting initialized. Another option is map the native controller to a secondary address space, then disable the DMA GATE # via the DOR disabling the DMA GATE #. This assumes that the native controller is switchable to a secondary address space.

10.4 Replacing the 820775L with a 82078 in a 5.OV Design

The 82078 easily replaces the 5.0V 82077SL with minimum design changes. With a few exceptions, most of the signals are named as they were in the 82077SL. Some pins were eliminated and other renamed to accommodate a reduced pin count and smaller package.

The connections to the AT bus are the same as the 82077SL with the following exceptions: MFM and DENT have been replaced by IDENT1 and IDENT0 The PLL0 pin was removed. Configure the tape dnve mode on the 82078 via the Tape Drive Register (TDR).

The Drive Interface on the 82078 is also similar to the 82077SL except as noted: DRVDEN0 and DRVDEN1 on the 82078 take the place of DENSEL, DRATE0 and DRATE1 on the 82077SL. The Drive Specification Command configures the polarity of these pins, thus selecting the density type of the drive. The Motor Enable pins (ME0-3) and the Drive Select pins (DS0-3) are renamed FDME(0-3) and FDS(0-3) respectively on the 82078. 10K pull-up resistors can be used on the disk interface. See Figure 10-3 for a schematic of the connection.

Pin Changes on the 64 Pin Part:

INVERT# is removed
4 NC's (no connects) are removed
MFM, IDENT pins on the 82077SL have been changed to IDENT1 and IDENT0 respectively.
PLL0 pin, which allowed for H/W configuration of tape drive mode is no longer available. Tape mode can be configured via the TDR register.
DENSEL, DRATEl, DRATE0 pins have been substituted by DRVDEN0, DRVDENl. the Drive Specification command can be used to configure these pins for various requirements of drives available on the market.
RDGATE has been added and can be used for diagnostics of the PLL.
MEDID1 MEDID0 are new, they return media type information to the TOR register.
DRVID1, DRVID0 return drive type information to the TDR register.
SEL3V# selects between either 3.3V or 5V mode. Connecting the pin LOW selects 3.3V mode.
5 VSS pins, 2 VCC pins. 2 VSSP pins, 1 VCCF pin, and 1 AVCC and 1 AVSS pin.
VCCF can be used to interface a 5.0V or a 3.3V drive to the 82078 (when SEL3V# is low).
The Hardware RESET pulse width has changed from 170 times the oscillator period to 100 ns plus 25 times the oscillator period.