![[INTEL NAVIGATION HEADER]](../../PIX/HEADER.GIF){kind=small}
A1. The 82091AA is an integrated single chip I/O solution containing a floppy disk controller (82078), 2 serial ports (16550 compliant), a multi-function parallel port (supports all IEEE Standard 1284 protocols (ECP, EPP, Byte, Compatibility, and Nibble)), an IDE interface (8- or 16-bit programmed I/O and 16 bit DMA), and a Game Port (a chip select port).
Q2. What is it used for?
A2. The integration of these I/O devices results in a minimization of form factor, cost, and power consumption. The 82091AA includes power management and 3.3V capability which are important for notebook applications. The 82091AA supports both motherboard and add-in card configurations.
Q3. Are there any Ap Notes, Tech-Bits, or errata?
A3. The following information is available:
A4. The IDE interface supports 8- or 16-bit programmed I/O and 16-bit DMA. The Host interface is an 8-bit ISA interface optimized for type "F" DMA and no wait state I/O accesses.
Q5. Is a 48MHz crystal required to support a 2.88Mbyte floppy?
A5. No. The 82091AA uses only a 24MHz crystal.
Q6. Are there any TAPI drivers for the 82091AA? Are there any drivers available?
A6. There are no special drivers needed. Any standard ATAPI driver should work.
Q7. Is the 82091AA IEEE1284 compliant? What are the differences?
A7. The IEEE1284 specification is evolving but the 82091AA functionality is "locked in silicon". The differences are listed:
A8. No, 2Mbps data rate for tape drives was not included into the 82091AA due to the rarity of the technology at the time of the device's production. The majority of tape drives uses either 500Kbps data rate or 1Mbps data rate and the AIP supports all of these current tape drives. The elimination of the 2Mbps data rate from the 82091AA also removes the need for the 48MHz clock; only a 24MHz oscillator is required. For customers interested in 2Mbps data rate functionality, we recommend the 82078-1.
Q9. Will the 82091AA work if the oscillator is less than 24MHz? How much less than the spec is allowable (+/- 0.1%)? Will the PLL fail on the floppy disk controller? What other problems will occur? Would the simple decode logic (IDE, standard parallel port) be affected?
A9. As the clock is run at lower and lower frequencies, the PLL will tend to run at lower and lower bias levels. This will eventually lead to truncated negative capture range in the floppy disk controller. Also, it will have a hard time reading disks written or formatted at above center frequency. The disks it produces will be skewed to the low side, making it harder for other PLLs to read them. As a result, inter-changability suffers. These issues are only significant at differences of @0.5% and higher error levels. The serial port also uses the clock for its baud rate. This adds to the error already present. The parallel port uses the clock, but only the ECP timing specs will change. There is no "bad" effect on the parallel port functions and the standard parallel port, IDE, and Host decodes are not affected- they don't need the clock. Most frequency synthesizers have about 0.14% error. This is probably insignificant. It is wise to stay within the range of 0.1% to 0.2% of the 24MHz center frequency.
Q10. What is the Microsoft(TM) ECP Compliance Test?
A10. It is a software and hardware package that allows testing of the 82091AA for compliance with the Microsoft(TM) ECP (Extended Capabilities Port) functions. Two 82091AA devices are added as target and source in the same system for testing and development purposes. There test package includes executables files and a description documents. The ECP Compliance Test is available from Microsoft(TM) or Intel.
Q11. What causes the application to fail the REGISTER test within the ECP Compliance Software. What does this test do?
A11. The Register test in the ECP Compliance software looks, among other things, at the bit settings in the ECPCFGA register. ECP Compliance Software rev.4.02 and later look and accept bit7 (hardwired to "1" for both edge and level triggered environments). See Q8 above.
Q12. What causes the application to fail the TESTMODE test within the ECP Compliance Software? What is the error message "0 INT received, nothing on IRQ, expected exactly 1?"
A12. The ECP Compliance Software requires two 82091AA devices within one system. There are two possible things that may be causing this failure if the development system is configured correctly:
1. The proper interrupts are not set. Go into debug and set addr 20 to 278 or 378.
2. The proper jumpers are not set relative to the DMA channels. In this situation, this means the dialog box entrees in the software must reflect the actual hardware settings.
Q13. Does the floppy disk controller on the 82091AA always mask out the 3F6h? Is there a way around this?
A13. Yes, the floppy always masks out 3F6, and yes, there is a way around this. See the Techbit/errata titled "Designing with the shared Floppy and IDE Register (3F7)".
Q14. Is it possible to use the IDE in PCMCIA and also use the floppy disk controller on the 82091AA?
A14. Yes, by using ATA PCMCIA drives, even though IDE is enabled on the 82091AA. Currently, there is no ISA PCMCIA which has IDE connectors. If such hardware does exist, the IDE controller must drive bits 0-6, not bit 7, to comply with PCMCIA specs.
Q15. If the 82091AA's floppy disk controller is enabled, can an external IDE controller be added?
A15. See the Tech-Bit: "Designing with the Shared Floppy and IDE Register (3F7)".
Q16. In what applications would I add the external buffers to the PPDIR signal?
A16. The PPDIR signal should have external buffers added if external ESD is a problem.
Q17. Should DATASTR generate a strobe whenever it is read or written? For example, 00H.
A17. DATASTR is described in the data book. Since the default value is 00h, it does not strobe if this value is read from or written to it.
Q18. The 82091AA is used in two drives (2.88MB FDD) support application. Drive assignments Drive 0= FDD_A/ Drive 1= FDD_B or Drive 0= FDD_B/ Drive 1= FDD_A causes CRC errors. System BIOS allows the system to select the bootable drive (FDD_A or FDD_B). What may be the problem?
A18. Insure that the FCFG1 register is set for two-drive support. Check the bits in the DOR register to insure that the motor enable bits and the drive select bits are set to match each other at the time the FDD_A and FDD_B are changed. Make sure bit 1 in the TDR register is set to 0. When the BIOS selects the bootable drive, bit 2 in the TDR has to change appropriately.
Q19. Can the 82091AA support a bi-directional STROBE# pin signal ?
A19. Actually, the equivalent of the STROBE# pin on other similar devices can be tied to allow the pin to be read rather than reading what was written into particular registers associated with this pin. The 82091AA does not have this exact capability. The PCON register in the EPP Mode, using the EPP parallel interface protocol, does not allow software control of the STROBE# bit. When programming this register in the EPP Mode, write the STROBE# Control bit (STROBEC) to 0 to allow for the parallel port handshake to operate properly. Also, the PCON register in the PS/2 Compatible Mode allows software to control the STROBE# bit. In the PS/2 Compatible Mode, the STROBE# Control (STROBEC) bit controls the AIP STROBE# signal. The STROBE# signal is set active to instruct the peripheral to accept the character being presented on the data lines. When STROBEC=1, the STROBE# signal is asserted. When STROBEC=0, the STROBE# signal is inactive. Bit 0 in the PCON register can be written and read in either configuration. The STROBE# signal in the 82091AA is an output only and is controlled by the STROBEC bit in the PCON register. The output on the STROBE# pin and the function of the STROBEC bit in the PCON register both vary according to the mode being used.
Q20. When the parallel port is configured to be bi-directional, are both data and control lines bi-directional?
A20. Only the data lines are bi-directional. In the ISA-compatible mode, even the parallel port data bus is uni-directional. The Nibble protocol permits data transfers from the peripheral device by using four peripheral status signal lines to transfer 4 bits of data at a time.
Q21. Does the CFGINDX get over-written when the CFGTRGT is written?
A21. The CFGINDX is an 8-bit register which contains the address index of the AIP configuration register to be accessed. CFGTRGT is a port for reading data from or writing data to the configuration register whose index address matches the address stored in the CFGINDX Register. Reading or writing the configuration target port does not over-write the configuration index register.
Q22. What does the RESET do to the contents of the Configuration Index Register?
A22. The CFGINDX Register has a default value of 00h following a RESET.
Q23. Is the address decode for AIP resisters the full 11-bit decode inside the AIP for all of the registers? What about IDE i/f registers (1F0~1F7H)?
A23. The AIP registers are 8-bit registers. The ISA address space uses SA0-SA9. The AIP decodes the 10-bit ISA address for the AIP registers. This is also true for the IDE primary interface address at 1F0-1F7. SA10 is used with SA0-SA9 extended register set of the ECP port. Since you mentioned the IDE drive, the IDE primary address space is 1F0-1F7. The floppy disk controller primary address is 3F0-3F6, but 3F7 is shared with the IDE drive. Please look at the 82091AA tech bit titled, "Designing with the Shared IDE and Floppy Register (3F7)".
Q24. Is the DCD pin tri-stated on loop-back mode or is it susceptible to noise?
A24. When the device is put into loop-back mode, there is an automatic MUX inside the device to allow the loop-back process. Any floating input pins will draw additional current but the fact that they are floating should not affect the device operation. Weak pull up/down (opposite the active state) for unused pins are suggested in any application.
Q25. (a.) Is the TC input necessary for a DMA transfer? (b.) Can I terminate a DMA transfer by disabling the DMAEN bit instead of using TC? Any probable errors?
A25. (a.) The TC input is normally asserted by the system DMA controller to indicate it has reached the last programmed data transfer. TC is accepted only if FDDACK# or PPDACK# is asserted. However, there is another technique: (b.) The Extended Control Register (ECP Mode) has a DMA Enable bit (DMAEN). When DMAEN=1, DMA is enabled and the host uses PPDREQ, PPDACK, and the TC pin to transfer data. When DMAEN=0, DMA is disabled and the PPDREQ output is tri-stated. In this case, programmed I/O is used to transfer data between the host and the AIP FIFO. The Service Interrupt (bit 2) needs to be set to "0" to allow generation of a TC interrupt. This bit must be written to "0" to reset the TC interrupt. There should be no errors using this technique if the programmed I/O is correct and the Service Interrupt bit 2 is reset accordingly.
Q26. How is the 2Mbyte/sec parallel port directional data transfer calculated? How is it measured? Is the data transfer speed limited by the other devices in the system? I have AIP parts that work faster. Will they all work faster?
A26. 2Mbyte/sec was a target spec based on application information at the time the AIP was designed. This transfer speed is limited by other devices in the application. Some AIP devices may work faster than 2Mbyte/sec but Intel will not guarantee data transfer rate above 2MB/s. The 2MB/s data rate transfer speed is not actually tested. What is tested is that the strobe goes active/inactive quickly enough and that the handshakes happen fast enough to guarantee the 2Mbyte/sec data rate. The 82091AA was designed so that if only a small amount of logic (like an inverter) is in the circuit external to the device, the AIP parallel port can dump bits into space free running and still handle it.
Q27. The 82091AA Design Guide contains some design examples. Capacitors are added to the serial port connection on one of the schematic but not the other. Why? What is the purpose of these capacitors?
A27. The capacitors on the serial port connections in the AIP Design Guide were placed there in an attempt to comply with the FCC compliance- protection against radiated/magnetic interference. The capacitors shown in the design guide examples are optional.
Q28. Does Power Management exist for IDE functions in the 82091AA?
A28. No. Power down management only exists for the serial ports, the parallel port, and the FDC.
Q29. Is there an external (pin) signal which can be used to turn off/power down the FDC?
A29. No. The only way to set the FDC to the power down mode is by configuring the proper registers.
Q30. Interlink is one of the DOS utilities/commands in MS-DOS 6.22. It is like Laplink, in that it lets you transfer files between two PCs. The parallel port, in this case, is set up as a standard parallel port, not bi-directional. However, Nibble mode of the 82091AA allows the use of the status lines of the parallel port as input back into the parallel port, thus enabling two-way communications. Has the Nibble mode been tested and used with the Interlink command in MS-DOS 6.22?
A30. The nibble mode function is tested on every device. The SV/CV was done on MS-DOS6.0 and the parallel port was checked using the LapLink software associated with MS-DOS6.0. The Interlink command should be the same in subsequent revisions. Concerning the tests done with Laplink: Laplink was used to transfer files between an i386 based system using a competitor's I/O chip and an i486 system using the 82091AA AIP. Files were transferred successfully to and from each computer. Laplink software can use a serial port or a parallel port for data transfers and tests were performed with both types of ports. Laplink worked for parallel port transfers at addresses 378H and 278H, and at both IRQs. The 82091AA was not tested with the INTERLNK.EXE MS-DOS6.21/6.22 utility because that software was not available then. The bottom line is simply how does the BIOS on the customer's platform (or MS-DOS6.22 drivers) set up the AIP? The AIP parallel port in many BIOS's defaults to the Centronics print mode. There has to be software in the PC to initialize the 82091AA and its parallel port to the desired modes. Also, the initialization software for one company's I/O device may not work on another company's device.
Information in this document is provided in connection with Intel products. Intel assumes no liability whatsoever, including infringement of any patent or copyright, for sale and use of Intel products except as provided in Intel's Terms and Conditions of Sale for such products. Intel retains the right to make changes to these specifications at any time, without notice. Microcomputer Products may have minor variations to this specification known as errata.
©INTEL CORPORATION, 1995
Legal Stuff © 1997 Intel Corporation