Mobile Pentium® Processor Family Product Brief

Product Highlights

• New and improved mobile Pentium processor for even better multimedia & communications performance.
• Highest performance member of the mobile Pentium processor family
  • Increased performance on current software
• Available at both 150 and 166 MHz
• First mobile microprocessor with Intel MMX technology
• Several micro-architectural enhancements over the original mobile Pentium processor
  • Doubled code and data caches to 16K each
  • Improved branch prediction
  • Enhanced pipeline
  • Deeper write buffers
  • Supports Intel MMX technology
• Fully compatible with all software written for the Pentium processor, Intel486™ processor, and Intel386™ processor

The mobile Pentium processor with MMX technology is a significant addition to the mobile Pentium processor family. Available at both 150 and 166 MHz, it is the first mobile microprocessor to support Intel MMX technology. The mobile Pentium processor with MMX runs current software faster than the original mobile Pentium processor at the same clock speed. Software designed for Intel MMX technology unleashes the additional performance provided by Intel MMX technology; enabling more colors, more realistic graphics, full-screen, full-motion video, and other multimedia enhancements. The improvement will be determined by the type of application, and the degree to which it has been designed for MMX technology. Intel’s media benchmark, which measures multimedia performance, runs faster on a mobile Pentium processor with MMX technology than it does on the original mobile Pentium processor at the same clock speed.

The mobile Pentium processor with MMX technology is both software and pin compatible with previous members of the mobile Pentium processor family. It contains 4.5 million transistors and is manufactured on Intel’s enhanced 0.35 micron process. This process uses CMOS and voltage reduction technology for low power and high density. This enables the mobile Pentium processor with MMX technology to remain within the thermal envelope of the original mobile Pentium processor while providing a significant performance increase.

The mobile Pentium processor with MMX technology is the newest addition to the mobile Pentium processor family and offers several micro-architectural enhancements over previous members.

• Doubled code and data caches to 16K each. On-chip Level 1 data and code cache sizes have doubled to 16KB each on the mobile Pentium processor with MMX technology. Larger separate internal caches improve performance by reducing average memory access time and providing fast access to recently-used instructions and data. The instruction and data caches can be accessed simultaneously while the dual-ported data cache supports two data references simultaneously. The data cache supports a write-back (or alternatively, writethrough, on a line by line basis) policy for memory updates.
  
• Improved branch prediction. Dynamic branch prediction uses the Branch Target Buffer (BTB) to boost performance by predicting the most likely set of instructions to be executed. The BTB has been improved on the mobile Pentium processor with MMX technology to increase its accuracy.
  
• Enhanced pipeline. To improve performance, an additional pipeline stage has been added.
  
• Deeper write buffers. A pool of four write buffers is now shared between the dual pipelines to improve memory write performance.
  
• Full support for Intel MMX technology. MMX technology is based on SIMD technique—Single Instruction, Multiple Data—which enables increased performance on a wide variety of multimedia and communications applications. Fifty-seven new instructions and a new 64-bit data type are supported in the mobile Pentium processor with MMX technology. All existing operating systems and application software are fully compatible with the mobile Pentium processor with MMX technology.

• Voltage Reduction Technology
  
• 320-Lead Tape Carrier Package (TCP) and 296-Pin Plastic Pin Grid Array (PPGA) package
  
• 60 MHz and 66 MHz bus speeds
  
• SL technology power management features
  
• 64-bit data bus
  
• Data integrity features
  
• A superscalar processor capable of executing two integer instructions in parallel in a single clock, achieving up to two times the integer performance relative to an equivalent frequency Intel486 CPU.
  
• A pipelined Floating-Point Unit (FPU) for supporting the 32- and 64-bit formats specified in IEEE Standard 754, as well as an 80-bit format. It is capable of executing two floating-point instructions in a single clock, achieving over five times the floating-point performance with instruction scheduling and overlapped (pipelined) execution. The FPU is object-code compatible with the Intel486 DX and Intel487 SX, Intel387 DX, and Intel387 SX math coprocessors.