8XC196KR/NT: Synchronous Serial I/O (SSIO) Port Timings

We currently do not have specifications for the SSIO in our datasheets, therefore this is to be used as a guide when utilizing the SSIO peripheral. The timings listed in Table 1 were obtained by lab analysis or by analysis of design. These timings are not tested in production, therefore are not guaranteed. The timings shown are based on the SSIO_BAUD register being equal to 80h, which is the fastest operation of the SSIO, and FFh, which is the slowest. For example, the KR at 16MHz will yield baudrates from 2MHz (80h) to 15.625KHz (FFh).

For more information on the SSIO, refer to the 8XC196KX User's Manual or the 8XC196NT User's Manual.

Table 1: SSIO Port Timings.

Symbol Parameter BRR=80H BRR=FFh Units

TCLCL Clock Period for SCn 8 Tosc 1024 Tosc ns

TCLCH Clock Falling Edge to Clock Rising Edge 4 Tosc 512 Tosc ns

TDVCH Input Data Setup to Clock Rising Edge 10 (min) ns

TCHDX Input Data Hold after Clock Rising Edge 2 Tosc + 40 (min) ns

TCLDV Clock Falling Edge to Data Out Valid 3 Tosc + 40 (max) ns

Note: The timings presented above are not tested nor guaranteed. They were obtained by lab analysis at room temperature or by analysis of design.

Signals: Conditions:

C = Clock L = Low

D = Data H = High

 V = Valid

 X = No longer valid

Figure 1: Waveform Diagrams

Table 2 lists sample code that uses SSIO channel 0 to continuously send data (AAh) to be received by SSIO channel 1. This is called `loop back mode', when both channels are connected together (ie- SC0 (master) connected to SC1 (slave) and SD0 (master) connected to SD1 (slave)). The code can be modified to send only one byte of data by clearing bit 2 (ATR) in the SSIOx_CON register.

Table 2: SSIO code which continuously transmits data from SD0 to SD1.

WSR EQU 014H:BYTE

SP_CON EQU 011H:BYTE

BAUD_RATE EQU 00EH:BYTE

P6_REG EQU 0D5H:BYTE

P6_DIR EQU 0D3H:BYTE

P6_MODE EQU 0D1H:BYTE

SSIO_BAUD EQU 0B4H:BYTE

SSIO0_CON EQU 0B1H:BYTE

SSIO1_CON EQU 0B3H:BYTE

SSIO0_BUF EQU 0B0H:BYTE

SSIO1_BUF EQU 0B2H:BYTE

RESULT EQU 122H:BYTE

CSEG AT 2080H

LDB WSR,#1FH ;window 1F

LDB P6_REG,#0C0H ;set ch1, clr ch0

LDB P6_DIR,#0C0H ;ch1=p/p, ch0=in

LDB P6_MODE,#0F0H ;special function

LDB SSIO_BAUD,#80H ;2M baud

LDB SSIO0_CON,#0CDH ;master_xmit

LDB SSIO1_CON,#0CH ;slave_receive

HERE:

LDB SSIO0_BUF,#0AAH ;xmit data `AA'

D_WAIT:

JBC SSIO1_CON,0,D_WAIT ;wait for received

STB SSIO1_BUF,RESULT ;store rec. data

SJMP HERE

END

Symbol	Parameter	BRR=80H	BRR=FFh	Units
TCLCL	Clock Period for SCn	8 Tosc	1024 Tosc	ns
TCLCH	Clock Falling Edge to Clock Rising Edge	4 Tosc	512 Tosc	ns
TDVCH	Input Data Setup to Clock Rising Edge	10 (min)		ns
TCHDX	Input Data Hold after Clock Rising Edge	2 Tosc + 40 (min)		ns
TCLDV	Clock Falling Edge to Data Out Valid	3 Tosc + 40 (max)		ns