For additional information about the Watchdog Timer, refer to the 8XC196KC/KD User's Manual (order #272238) or ApBUILDER software (order #272216).
The Watchdog Timer is a very useful peripheral that safeguards against software failures. The Watchdog Timer (WDT) is a 16 bit ripple counter that will reset the 8XC196KC/KD if the counter overflows. When the WDT is enabled, this peripheral monitors the execution of a program. This is useful when expensive hardware is being controlled. If we operate in an electrically noisy environment a noise spike can be potentially fatal to the operation of a microcontroller. We can maintain control in critical applications by resetting the microcontroller when a runaway software process hangs the system.
There is only one Special Function Register to concern ourselves with in this discussion. That register is called WATCHDOG.
To clear the WDT and enable it we must load WATCHDOG with 1EH followed immediately by E1H. This will initialize the WDT with a value of 0000H. We have 64K state times to clear the WATCHDOG register. One state time = [2/crystal frequency (MHz)]. For example, when using a 20MHz crystal, 1 state time is equal to 100ns. Essentially we have 64K*100ns or 65,535*100ns. This translates to about 6.55ms to clear the register. Once enabled, the only way to disable the WDT is to perform a reset.
Programming the WDT
The function of the WDT is to monitor software events. The programs listed at the end of this document demonstrate how the WDT functions. Even though the WDT is cleared based on the presence of an external event, in practice this is not done. It is used here only for demonstration purposes. Program listing 1 is written in ASM196 (assembly code) while listing 2 is written in C196 (C-code). Both programs continuously reset the WATCHDOG SFR to 0 as long as the value of IOPORT0 never equals 0. These values are continuously written to IOPORT1. If this program is run on an Intel 8XC196KC/KD Evaluation board or Project Builder board, IOPORT1 drives an LED bank. The value of IOPORT0 is always tested against 0. Once this value equals 0, we enter an infinite loop where the WATCHDOG SFR is never reinitialized. This results in a reset. As long as we are able to place a logic high on the pins of IOPORT0 we will never reset the 8XC196KC/KD. These two programs show how not reinitializing WATCHDOG will cause a reset.
Now that we have some insight as to where we are headed, we may begin programming the WDT. One of the first things we should do is set up the Stack Pointer (SP). The SP should be loaded with a value when programming in ASM196. In program listing 1, a value of 100H is used. If using C196 some of the initialization is already done for you, so this step is not needed. When reading or writing to the SFRs it is always important to be sure that you are in the correct horizontal window or Hwindow. For example, in order to access WATCHDOG, we should select Hwindow 0. We select this Hwindow by loading the WSR (Window Select Register) with 0. In order to clear and enable the WDT we need to load
WATCHDOG with 1EH then E1H. Now that we have the Watchdog Timer enabled we move the value of IOPORT0 to IOPORT1 or the LED bank. We continuously compare IOPORT0 with the value 0. If the register holds a value other than 0, we loop again and clear the WDT. If the register holds a 0 then we sit in an endless loop doing nothing. This will eventually cause the 16 bit ripple counter to overflow, causing a reset to occur.
Note: When using the Intel 8XC196KC/KD evaluation boards, make sure jumper E4 is in the AB position to allow IOPORT0 to be used on the analog input pins (JP1).
PROGRAM LISTINGS: Program listings 1 and 2 can be found in the files, BTBEVAL.EXE for evaluation boards and, BTBDEVEL.EXE for Project Builder boards on the Intel Bulletin Board Service in the MCS(R) 96 Family / General section.
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