One of the most confusing areas of bus design with the 8xC196 is the generation of wait states for slow external bus devices. The AC timing parameters associated with wait states are:
|TAVYV||Address Valid to READY Setup|
|TLLYV||ALE Low to READY Setup|
|TYLYH||Non READY Time|
|TCLYX||READY Hold after CLKOUT Low|
|TLLYX||READY Hold after ALE Low|
READY is sampled internally at the falling edge of CLKOUT approximately one TOSC after ALE falls. There is a tendency for designers to try to use ALE to generate READY. There is no reason to take ALE into account either for READY Setup or Hold. Ignoring ALE simplifies the design and only TAVYV and TCLYX need be taken into account in any wait state design. For a large number of wait state requirements, even TCLYX can be forgotten. Note that the address signals used to generate READY are valid long before the fall of ALE and feed directly through the transparent latches during ALE.
The following discussions will proceed from the simplest wait state requirement to a complex wait state generator. The following examples use the 8xC196KC 16 MHz AC timings. Note that wait states occur on the external bus only. All internal accesses are made at full speed.
WAIT STATES AND THE CHIP CONFIGURATION REGISTER
The CCR load (CCB fetch) is the first thing that happens in a 8xC196 system following RESET. The contents of memory location 2018H are loaded into the CCR. There are two bits of the CCR (IRC1=CCR.5 and IRC0=CCR.4) associated with wait states:
|0||0||Limit to one wait state|
|0||1||Limit to two wait states|
|1||0||Limit to three wait states|
|1||1||Wait states not limited internally|
The advantage of the first three configurations is that the user does not have to worry about taking READY back to a '1' to avoid an infinite number of wait states. As a matter of fact, if a constant one, two, or three wait states is required, READY can be tied low.
ONE WAIT STATE
The simplest wait state design is to have one wait state on every bus cycle. This configuration requires no wait state logic at all. Simply set IRC1 and IRC0 to '0' and tie READY low.
SELECTABLE ZERO OR 'n' WAIT STATES ('n' = one, two, or three)
The majority of wait state requirements can be satisfied with a selectable zero or 'n' wait states. Assume the following requirements:
|Address Range||Required Wait States|
|C000H-FFFFH||'n' = one, two, or three|
Set IRC1 and IRC0 to correspond to the wait state limit 'n' in the above chart. Add the following wait state/chip select logic and the requirements are satisfied.
Whenever A15='1' and A14='1', the output of the NAND gate will be '0' causing 'n' wait states (and chip select). Otherwise, the output of the NAND gate will be '1' resulting in zero wait states (and no chip select).
ONE WAIT STATE FOR WRITE, ZERO FOR READ
In some designs, a wait state is required for a write operation but not for a read operation. The bus devices do not know if there is to be a read or write operation until RD# or WR# occurs. Assume that the only thing on the bus is an EEPROM memory that requires one wait state for write and zero wait states for read. There are a couple of tricks that can be played to cause a wait state only on write operations:
If the WR# pulse width is just a little too short, here's another trick that will work. The AC timings for the 16 MHz 'C196KC are: TWLWH=TOSC-20=42.5 nS (WR# Low Period) and TWHQX=TOSC-25=37.5 nS (Data Hold after WR# Rising Edge). Most memories do not require 37.5 nS data hold time. In fact, many have 0 nS hold time values. Time can be taken away from TWHQX and given to TWLWH with the following circuit.
The 74AC08 has an eight nS propagation delay. The values for the resistor and capacitor are chosen to make the stretched WR# pulse longer than the WR# input by up to 29 nS ( 37.5 - 8 ). Thus WR# low pulses of up to 72 nS can be generated. The resistor value must be large enough to keep WR# from sinking too much current. A value of approximately 3.3K ohms is reasonable.
If the capacitor is chosen to be 10 pF, the resulting stretch will be approximately 33 nS. The precision resistor value should correspond to the exact timing needed. The capacitor should have a matched negative temperature coefficient so the RC time constant will not drift with temperature. WARNING: As the stretched pulse width approaches TWLWH+TWHQX-8, voltage and temperature variations and noise can cause the above circuit to malfunction. A safety pad of 10 nS would mean a maximum stretched pulse width of 62 nS.
A COMPLEX WAIT STATE GENERATOR
If the Chip Configuration Register (CCR) contains '1's in IRC1 and IRC0 (unlimited number of wait states), the wait state logic will be of traditional design. In addition to controlling the needed number of wait states, the wait state logic must also limit the number of wait states to something less than infinity.
This section will look at a conventional wait state design using PAL type logic. The logic diagrams are symbolic only and do not represent devices available in the SSI families.
The first piece of logic needed is a wait state counter. The CLKOUT from the 8xC196 is the clock input for the counter. The counter is reset by ALE. Each cycle of CLKOUT from falling edge to falling edge after ALE can be a wait state.
The above Wait State Counter has three outputs, WSC0, WSC1, and WSC2. This corresponds to zero through seven possible wait states.
The first step in a PAL implementation of the wait state generator is to design the above counter circuit. The PAL needs to contain at least three D-type flip-flops with asynchronous resets. After the Wait State Counter is designed we can proceed to the actual wait state requirements corresponding to the memory map.
A 22V10 PAL device is used to generate wait states on the 8xC196 Eval Boards. In addition to generating wait states, it also generates BUSWIDTH and chip selects, and does memory remapping. PALs are powerful devices and eliminate a lot of SSI packages.
After choosing memory and peripheral devices for a design, a bus timing analysis is necessary. A particular timing analysis might result in the following requirements:
|Wait||(Make READY=1 when these are True)|
Note that x = don't care. The address terms are normally the same as the chip select lines to the bus devices. Given the above conditions, one can write the Boolean equation for READY as follows:
|Address Range||States||Boolean Term for READY=|
What happened to the Address Lines in the last term? We do not want the counter ever to roll over. Seven wait states is the absolute maximum number so we make seven the default condition. If no other combinations are satisfied, we will default to seven wait states and never more than that.
After the designer has generated the wait state counter with a PAL, the READY Boolean equation is input to the PAL development software. Once the PAL is programmed to implement the wait state counter and generate READY, simply wiring in the necessary inputs, (CLKOUT, ALE, A15, A14, A13, and A12), yields a READY signal that satisfies the above requirements. Chip Select lines are also normally generated since those boolean terms are part of READY.
Note that we used ALE only for resetting the Wait State Counter. We did not qualify READY with ALE or wait until the end of ALE to generate READY. We must satisfy the TAVYV parameter but we can ignore TLLYV. TAVYV = 50 nS for the KB, at 16mhz, and 57ns for the KC, at 16 MHz. The PAL must be fast enough to propagate the address signals. This 50/57 nS value only applies for zero wait states. Once we generate at least one wait state, we have a whole clock period (125 nS at 16 Mhz for the KB and KC) to propagate a '1' into the READY input.
The following diagram represents what combinational logic is needed to generate READY along with positive true chip selects:
BOOLEAN LOGIC DIAGRAM
Of course the above logic could be implemented with 74xx logic, but it would not be cost effective and might not be fast enough. The PAL was invented and designed to accomplish functions like this and eliminates many packages of SSI type devices. The internal design of the PAL insures a minimum progagation delay that stage after stage of SSI logic can not match.
The operation of the Buswidth pin is very similar to the READY pin. ALE should not be used to qualify Buswidth. The different chip select signals are normally gated together to generate the Buswidth input. Like the READY signal, the Buswidth signal (TAVGV) must be valid, 50 nS for the KB and 57 ns for the KC, before the falling edge of CLKOUT. The same PAL that generates READY and the chip selects can be used to generate Buswidth.
If bit CCR.1 (Bus Width Select) is loaded with a '0', the 8xC196 is locked into eight-bit bus mode. However, if CCR.1 is loaded with a '1', the bus becomes dynamically configurable using the Buswidth pin input. Buswidth has approximately the same timing as READY. The state of the Buswidth pin is a don't care after the falling edge of CLKOUT following ALE.
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