The information found in this document pertaining to these product, 80C31BH, 80C51BH, 80C51BHP, 87C51, 80C32 and 80C52, are based on the P629 process that has an "A" suffix at the FPO number.

2.0 HMOS and CHMOS MCS51 Microcontrollers

HMOS Version	CHMOS Version
8031AH	80C31BH
8051AH 8051AHP	80C51BH 80C51BHP
8751H 8751H-8 8751BH	87C51
8032AH	80C32
8052AH	80C52
8752BH	87C52

Table 1. HMOS and CHMOS version of MCS 51 microcontrollers

In most cases, an 80C51BH can directly replace the 8051AH in existing applications. It can execute the same code at the same speed, accept signals from same sources, and drive the same loads. However, the 80C51BH covers a wider range of speeds, will emit CMOS logic levels to CMOS loads, and will draw about 1/10 the current of the 8051AH (and even lower current in the reduced power modes).

3.0 Logic Level

Symbol	8751H/8751H-8		80C31BH, 80C31BHP, 80C51BH, 87C51, 80C32, 80C52, 87C52		Units
	Min	Max	Min	Max
1/TCLCL	3.5	12.0	3.5	12.0	MHz
TLLAX	TCLCL - 35		TCLCL - 30		ns
TLLIV		4TCLCL - 150		4TCLCL - 100	ns
TLLPL	TCLCL - 25		TCLCL - 30		ns
TPLPH	3TCLCL - 60		3TCLCL - 45		ns
TPLIV		3TCLCL - 150		3TCLCL - 105	ns
TPXIZ		TCLCL - 20		TCLCL - 25	ns
TPXAV	TCLCL - 8		-N.A.-		ns
TAVIV		5TCLCL - 150		5TCLCL - 105	ns
TPLAZ		20		10	ns
TRHDZ		2TCLCL - 70		2TCLCL - 60	ns
TQVWX	TCLCL - 70		TCLCL - 50		ns
TRLAZ		20		0	ns
TWHLH	TCLCL - 50	TCLCL + 50	TCLCL - 40	TCLCL + 40	ns

Table 3b. AC specification group 2

5.0 Pin Mapping

The pin mapping for the DIP and PLCC package found in the 8031AH, 8051AH, 8051AHP, 8751H and 8751BH are identical to the pin mapping of the 80C31BH, 80C51BH, 80C51BHP and 87C51. For the PLCC package, the 80C31BH, 80C51BH, 80C32, 80C52 and 87C52 have one extra ground pin that is not available for the 8032AH, 8052AH and 8752BH. This extra ground pin is on pin1, VSS1. This pin help to reduce ground and improve power supply by-passing. Note: Connection of this pin is not needed for proper operation.

6.0 External Clock Drive

To drive the HMOS MCS 51 microcontroller with an external clock signal, ground the XTAL1 pin and drive the XTAL2 pin. To drive the CHMOS MCS 51 microcontrollers with an external clock signal, drive the XTAL1 pin and leave the XTAL2 pin unconnected. The reason for the difference is that in the HMOS devices, it is the XTAL2 pin that drives the internal clocking circuits, whereas in the CHMOS device it is the XTAL1 pin that drives the internal clocking circuits. The external circuits that uses the crystal resonator and 2 capacitor configuration together with the on-chip oscillator for the HMOS and the CHMOS devices are identical.

7.0 Unused Pins

Unused pins of Ports 1, 2 and 3 can be ignored in both HMOS and CHMOS MCS 51 microcontrollers. Unused Port 0 pins in HMOS version of the MCS 51 microcontroller can be ignored, even if they are floating. But in CHMOS version of the MCS 51 microcontroller, these Port 0 pins should not be left afloat. If they float, they tend to float into the transition region between 0 and 1, where the pullup or pulldown devices in the input buffer are both conductive. This causes a significant increase in Icc. These unused pins should be externally pulled up or down, or they can be internally pulled down by writing 0s to them.

8.0 Power-On Reset

For HMOS devices when Vcc is turned on, an automatic reset can be obtained by connecting the RST pin to Vcc through a 10uF capacitor and to Vss through a resistor. The CHMOS devices do not require this resistor although its presence does no harm. In fact, for CHMOS devices the external resistor can be removed because they have an internal pulldown on the RST pin. The capacitor value could then be reduced to 1uF.

9.0 Program Memory Protection

9.1 8051AHP and 80C51BHP (Information related to 87C51/80C51BH/80C31BH found in this document will be reflected in the new revsion datasheet (order # 272335-002).

The 8051AHP protection features are:

Program verification has been disabled
External memory access have been limited to 4K.

The 80C51BHP protection features are:

64 bytes of encryption array
MOVC instructions executed from external program memory are disabled from fetching code bytes from internal memory
EA is sampled and latched on reset.

9.2 8751H/8751BH/8752BH and 87C51/87C52

The 8751H protection features are:

Program verification has been disabled
External memory execution has been disabled.

The 8751BH/8752BH protection features have 32 bytes of encryption array and with and 2 programmable lock bits that when programmed according to Table 4 will provide different levels of protection for the on-chip code and data.

Program Lock Bits			Protection Type
	LB1	LB2
1	U	U	No program lock features enabled. (Code verify will still be encrypted by the Encryption Array)
2	P	U	MOVC instructions executed from external program memory are disabled from fetching code bytes from internal memory, EA is sampled and latched on reset, and further programming of the EPROM/OTP is disabled.
3	P	P	Same as 2, also verify is disabled.

Table 4 Program Lock Bits and the Features

The 87C51/87C52 protection features have 64 bytes of encryption array and 3 programmable lock bits that when programmed according to Table 5 will provide different levels of protection for the on-chip code and data.

Program Lock Bits				Protection Type
	LB1	LB2	LB3
1	U	U	U	No program lock features enabled. (Code verify will still be encrypted by the Encryption Array)
2	P	U	U	MOVC instructions executed from external program memory are disabled from fetching code bytes from internal memory, EA is sampled and latched on reset, and further programming of the EPROM/OTP is disabled.
3	P	P	U	Same as 2, also verify is disabled.
4	P	P	P	Same as 3, also external execution is disabled.

Table 5 Program Lock Bits and the Features

Legend:
U Unprogrammed
P Programmed

10.0 Timer 2

Timer 2 operating features (16-bit auto-reload, 16-bit capture and baud rate generator) found in 8032AH/8052AH/8752BH are also available in the 80C32/80C52/87C52. There are 2 additional features, 16-bit auto-reload with up or down counter and programmable clock-out that are available only in 80C32/80C52/87C52.

11.0 Power Management

For applications where power consumption is critical the CHMOS version provides power reduced modes of operation as a standard feature. The 80C31BH/80C51BH/80C51BHP and 80C32/80C52/87C52 CHMOS version of MCS 51 microcontroller have two power management modes, and these are Idle Mode and Power Down Mode.

12.0 Interrupt Priority Levels

The HMOS devices has only one Interrupt Priority register (IP) that allows two interrupt priority levels. But the CHMOS version provides the IP register and a second Interrupt Priority register (IPH) that allows four interrupt priority levels.

13.0 Power Off Flag

The Power Off Flag (POF), bit 4 in the Special Function Register PCON (PCON.4) is only available in the CHMOS devices. POF is set by hardware when Vcc rises from 0 to 5 Volts. POF can also be set or cleared by software. This allows the user to distinguish between a "cold start" reset and a "warm start" reset. Note: Vcc must remain above 3 Volts for POF to retain a 0.

14.0 Asynchronous Port Reset

To reset the HMOS devices port pins, the oscillator must be running. At least 19 oscillator periods must occur after a logic 1 is applied to the RST pin before the port pins are driven to their reset state. For the CHMOS devices, the clock does not have to be running for the ports to assume their reset value. The port pins are driven to their reset state as soon as a valid high is applied to the RST pin.

15.0 Enhanced Serial Port

The serial port automatic address recognition and framing error detection are available only in the CHMOS devices. The automatic address recognition feature when enabled will set the Receive Interrupt (RI) flag only when the received byte corresponds to either a Given or Broadcast address. The automatic address recognition feature will reduce the CPU time required to service the serial port. The Framing Error (FE) detection allows the serial port to check for a valid stop bits in mode 1, 2 and 3. A missing stop bit can be caused, for example, by noise on the serial lines, or transmission by two CPUs simultaneously.

16.0 Reference

1. Designing with the 80C51BH , Application Note AP-252,
2. MCS 51 8-Bit Control-Oriented Microcontrollers
3. 87C51/80C51BH/80C31BH CHMOS Single-Chip 8-Bit Microcontroller,
4. 8xC52/54/58 CHMOS Single-Chip 8-Bit Microcontroller

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