This book provides technical information pertaining to the 82496/82497/82498 cache controller and the 82491/82492/82493 cache SRAM chip sets. The 82498/82493 second-level cache chip set is new to this edition and its interface to the Pentium(R) processors at iCOMP(R) index 1110/133 mhz, 1000/120 Mhz, 815/100 Mhz and 735/90 Mhz are discussed in detail. Other information covered in this manual includes: cache architecture, cache consistency protocol, electrical, mechanical and thermal specifications.
The Pentium processor may contain design defects or errors known as errata. Current characterized errata are available on request. For the latest Specification Update containing this information, contact the Intel Literature Center at 800-548-4725 in the U.S and ask for the Pentium(R) Processor Specification Update (Order Number 242480). In other geographies, please contact your local sales office.
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