INTEL NAVIGATION HEADER

AB-33 Memory Expansion for the 8096

This Application Brief presents two examples of a paging scheme for the 8096, allowing either 256K bytes of total memory, or 544K bytes of total memory. Both systems utilize PORT1 as the output for the upper ad- dress lines. Because Interrupt vectors, and other critical sections of code must always be present, addresses 0-7FFFH always refer to the same main page. The PORT1 upper addresses only affect addresses 8000- FFFFH, by slapping several 32K pages in and out.

355514 bytes
27052201.pdf


Legal Stuff © 1997 Intel Corporation

Free Web Hosting