This document identifies the issues associated with accessing and testing signal pins in a Ball Grid Array (BGA)
package. Identified herein is one approach to accessing the signal pins in a BGA package.
This document defines a standard connector which facilitates interface between the i960® Rx I/O Processor and an
In-Circuit-Emulator (ICE) or a Logic Analyzer (LA). The document provides information about the connector, its
layout and identifies signal pins required to provide debug capability on the i960 Rx I/O Processor. Also included is a
sample routing of signal pins from the processor to the connector.
This revision is currently available to customers who are designing this capability into their systems. A future
revision of this document will be widely available as an application note.
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