This application note describes a DRAM controller for use with Intels i960 ® JA/JF/JD microprocessors. Other application notes are available which describe DRAM controllers for the i960 CA and CF processors. This application note contains some general DRAM controller theory as well as this designs state machine definitions and timing diagrams. It also contains the PLD equations which were used to build and test the prototype design.
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27267401.pdf
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