This application note describes a DRAM controller for use with the i960 ® CF 40 MHz microprocessor. Other application notes are available which describe DRAM controllers for the i960 Cx and Jx processors. This document contains some general DRAM controller theory as well as this designs state machine definitions and timing diagrams. It also contains the PLD equations used to build and test the prototype design.
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27265501.pdf
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