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Local area networks (LANs) have changed dramatically in the two decades since Intel, Xerox, and Digital Equipment Corp. helped define the Ethernet standard. The original sin-gle- megabit Ethernet standard called for a simple bus topol-ogy, where end nodes were connected in a simple chain fashion, and LAN segments were bridged together when any one workgroup LAN became too full. In the mid-1980s, a simple controller chip architecture with some dedicated logic for carrier-sensing protocols could suffice for most Medium Access Control-layer processing. The finalization of the 10-Base T Ethernet standard forced a radical change in LAN architectures in the late 1980s. While the shifts to 10-Mbit/sec speeds and unshielded twist-ed- pair wiring as a physical medium were both significant, the specification of a star-based topology helped give rise to the world of hubs, routers, and switching hubs that define the internetworking market today. Ethernet was specified as a hub - instead of a bus - with a concentrator at its center. Despite a few detours into fault resilient rings in the token ring and Fiber Distributed Data Interface standards, the shift to hub-based workgroup LANs has reconfigured the net-working landscape permanently. To connect every desktop, the new goal of internetwork-ing vendors is to provide all single-protocol LAN bridging and multiprotocol routing in one central routable hub. The demands placed upon the hub controller are tremendous, as packets must be processed and often encapsulated for deliv-ery to a remote LAN segment. The arrival of two new types of switching standards, switched-segment LANs and Asynchronous Transfer Mode (ATM) networks, have further increased the performance required from internetworking equipment. When startups such as Cisco and Wellfleet formed the router industry at the end of the 1980s, the companies relied on proprietary bit slice processors or multiprocessing banks of CISC processors to accelerate packets at latencies low enough to meet enterprise networking demands. By the mid-1990s, these techniques were no longer adequate to handle the combined needs of routing and switching. Vendors had to rely on developing more and more ASICs to add dedicat-ed protocol acceleration logic and ease packet-to-cell con-version at the ATM/LAN interface. A significant number of OEMs in the networking market have discovered a simpler answer to their problems - the high performance architecture of the Intel i960 (R) 32-bit embedded processor
The i960 processor was designed to handle multiple data types quickly and efficiently in embedded applications such as internetworking. Early versions, such as the i960 KA/KB processors, became the processors of choice for data-inten-sive applications such as imaging and packet processing. With the advent of the superscalar i960 CA/CF proces-sors, the performance advantages of the architecture over-whelmed other CISC and RISC competitors in the internet-working field. The i960 CA/CF processors offer a super-scalar design featuring four processing units. Fast instruc-tion issuance and on-chip buffering allow the processor to find equal utility in an environment of variable-sized frame or like-sized cells. The CA processor offers a 1 Kbyte two-way set associative instruction cache while the CF processor offers a 4 Kbyte two-way set associative instruction cache and a 1 Kbyte direct mapped data cache. Both processors also offer a 1 Kbyte on-chip data RAM, 4 DMA channels, and a flexible interrupt controller on-chip. Intel's newest members of the i960 architecture, the Hx series, have been specifically designed for internetworking applications to provide even higher processing capabilities. The instruction cache has been expanded to 16 Kbytes, the data cache has been expanded to 8 Kbytes, and the data RAM has been expanded to 2 Kbytes. These larger caches allow more code to be resident in on-chip RAM providing faster program execution. Several new instructions such as byte swap, cache invalidate, conditional adds and subtracts, and a new compare instruction also contribute to greater performance. In addition, the Hx series offers lower power consumption by supporting 3.3 V designs. The new Hx series also has been designed with Intel's clock multiplier technology allowing a variety of code and pin compatible components to be offered at various price/per-formance points. The HA features bus and core speeds of 25, 33, and 40 MHz with a peak MIPs rating of 80. The HD fea-tures a clock doubled core with external bus speeds of 16, 25, and 33 MHz with corresponding core CPU speeds of 32, 50, and 66 MHz. The HD has a peaks MIPs rating of 132. The HT features a clock tripled core with external bus speeds of 20 and 25 MHz and a core CPU frequency of 60 and 75 MHz offering a peak MIPs rating of 150.
In a real world network, packet data is often unaligned. Because data frames can be of variable size, processing of unaligned data can be a major bottleneck, even in traditional Ethernet repeaters and hubs. The i960 architecture is unique among most RISC architectures in providing hardware sup-port for such unaligned data, in both big and little endian formats. Thus unaligned data is handled quickly and effi-ciently in hardware, without having to use the much slower method of faulting and executing microcode as is common in other RISC processors. Another data related problem is byte ordering. Desktop PCs based on Intel microprocessors use little endian byte ordering while Motorola and many RISC based systems uti-lize big endian ordering. A network accepting data from both environments must support dual-byte ordering. Beginning with the i960 CA processor and continuing through the Hx series, the i960 architecture expertly handles both big endian and little endian byte ordering, effectively handling data from a variety of network sources. The true test of a processor is not how good it looks on paper, but how it performs in your actual product solution. One significant indicator of satisfaction in this area is the number of customers currently using the i960 architecture. In 1993, the i960 processor architecture outshipped all other RISC vendors combined, making the i960 architecture the leading processor architecture in the networking industry today (source: Dataquest).
The i960 processors are used in a great variety of products in the internetworking market. IBM uses the processor in projects ranging from its ARTIC* interface board to its 25- Mbit ATM cards where the i960 is used as a segmentation-reassembly accelerator. Fore Systems Inc. uses the i960 processor as a coprocessor in its 200 series of ATM end-node adapters. Ungermann-Bass Inc. chose the i960 proces-sor for the switch processing element in its DragonSwitch* architecture for switched Ethernet. Retix Inc. uses the architecture as a multiprotocol routing engine. Net Edge Systems Inc. uses multiple i960 processors in several partitioned tasks in its ATM Connect* router. Cabletron Systems Inc. uses the i960 architecture at the heart of its Multimedia Access Center-PLUS (MMAC-PLUS) hub. The Artel Galactica* switching hub, recently acquired by Chipcom, relies on the i960 processor for switch processing. These are just a few of the many examples of customers who use the i960 processor in products. From small adapter card companies, to large hub vendors, the i960 architecture is embraced as the preeminent solution for internetworking products. The diversity of this customer list is self evident. The i960 architecture provides the flexibility to handle an assortment of packet- and cell-processing tasks. It is equally at home in switching hubs, multiprotocol routers, inverse multiplexers, ATM workgroup switches, and time-division bus systems. The i960 architecture is your best solution for a variety of network operations.
A key factor in selecting an architecture for many cus-tomers is the quality and support provided by the develop-ment tools environment. With today's fast paced product development cycle, quick time-to-market has become the expected standard. The i960 architecture is supported by more than 70 vendors offering over 200 support tools and services designed to speed your product to market. The Intel Solutions960 ® program acts as a customer support center to assist in vendor and product selection, to provide "real-life" application development examples, to showcase customer solutions, to provide information on new development prod-ucts and services, and to insure the i960 architecture is sup-ported by a world class development environment. The Solutions960 program also highlights networking and other co-processor products that can be interfaced to the i960 architecture to simplify design and development. The i960 architecture is supported by the industry's only profile-driven, optimizing compiler. This compiler further reduces development time by eliminating the need to manually opti-mize code. It also increases application performance by up to 30 percent by optimizing code and exploiting the i960 architecture such as storing key variables in the on-chip data RAM. The i960 processor development environment pro-vides the high quality tools and support you need to bring your product quickly to market.
Intel invests hundreds of millions of dollars into research and development each year to maintain its technological leadership in the integrated circuit market. Let us put this investment to work for your company. Please contact your Intel representative or distributor today for more informa-tion on getting started on your design with the Intel i960 architecture.
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