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TimingDesigner* (Flash Support)

Chronology


Architecture:
Type :
Last Update:

FLASH Bulk-Erase_Component
Modeling/Simulation
3/14/97 2:49:00 PM

Vendor Information



Tool Description:

TimingDesigner* is software for accurately modeling, visualizing, analyzing, and documenting digital circuit timing.
Over 10,000 engineers at almost every major electronics company in the world use TimingDesigner. It's the most widely used timing specification and analysis software ever developed.
TimingDesigner is used with any type of design - chip, board, or system - where timing is important, or where accurate timing and interface specifications must be communicated to others.
TimingDesigner models complex digital circuit timing by combining an interactive timing diagram editor with a special-purpose timing spreadsheet.
The engineer first creates a timing diagram with the timing diagram editor, which shows the waveforms (sequence of events), delays (cause-and-effect relationships), and timing constraints of a proposed design.
The spreadsheet is then used to enter the min/max values of each delay and constraint. These values may be complex formulas - including min/max variables - so that path delays, different rise/fall times, loading, temperature, and other effects can be accurately modeled.
After each modification, TimingDesigner's static timing engine traces all of the delay paths specified in the timing diagram, removes common delays, adjusts for delays which track, selects the critical paths, and then computes the worst-case timing margins by comparing the total delay
along each critical path to the minimum or maximum allowable value specified in each constraint.
One of the things engineers like best about TimingDesigner is that the effects of design changes are seen instantly. Far more alternatives can be evaluated in a short time than with any other method.

Tool Features:

  • Create and analyze timing diagrams

  • Compute worst-case timing margins

  • Instantly see the effects of design tradeoffs

  • Analyze the interface between complex chips

  • Visualize timing relationships in complex clock trees

  • Communicate timing specifications to other designers

  • Works with QuickBench* and Synchrony*
  • File Attachments:

    SOLF_038.PDF - SolutionsFlash Memory Catalog Product Listing

    Supported Device Detail Matrix:

    Part & Package

    Revision

    Status

    Availability

    28F010 - Plastic Dip-32 ld
    28F010 - PLCC-32 ld
    28F010 - TSOP-32 ld
    28F010 - TSOP-32 ld(R)
    28F020 - Plastic Dip-32 ld
    28F020 - PLCC-32 ld
    28F020 - TSOP-32 ld
    28F020 - TSOP-32 ld(R)

    1.0
    1.0
    1.0
    1.0
    1.0
    1.0
    1.0
    1.0

    Released
    Released
    Released
    Released
    Released
    Released
    Released
    Released

    3/8/96
    3/8/96
    3/8/96
    3/8/96
    3/8/96
    3/8/96
    3/8/96
    3/8/96



    Vendor Information:


    Chronology

    8405 165th Avenue N.E.
    Redmond , WA 98052
    USA
    (800) 869-4227

    Fax : (206) 869-4229
    Toll Free : (800) 800-6494
    URL : http://www.chronology.com

    Contact the vendor above for the latest Distributor information




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