[INTEL NAVIGATION HEADER]

Intel Architecture"> High Value 16 Mb
High Value 32 Mb
High Value 4 Mb
High Value 8 Mb
High Integration 1Mb
High Integration 2Mb
High Integration 4Mb
High Integration 8Mb">

AB-66 Resolving Bus Contention When Interfacing the Intel386(TM) EX Embedded Processor with Intel Flash

Examining the worst-case timing relations for interfacing the Intel386(TM) EX embedded processor with flash indicates bus contention on a memory read followed by a memory write. However, the Intel386 EX embedded processor specification t50 resolves this issue and guarantees no bus contention if the flash data float time (tGHQZ) is <= t50. This document explains why there is no contention when interfacing with Intel Flash.


File Name/Size:
29219701.pdf
52576 bytes
Download From:
Developers' Insight CD-ROM


Legal Stuff © 1997 Intel Corporation
Free Web Hosting