Embedded Intel 186 Microprocessor Family Frequently Asked Questions


Q. If there is no minimum spec. shown, should I assume 0?
A. Yes.

Q. When PCS5# and PCS6# are used for latched A1 and A2, what are the timings?
A. The timings are the same as for the chip selects.

Q. Are the chip select lines glitch-free?
A. Yes. Take data sheet at face value.

Q. Can I assume that the timings are guardbanded and stretch the specs a little?
A. The days of very conservative guardbanding are past,especially at higher speeds. In some cases the factory has enough data to offer advice.

Q. Is it fair to assume that unrelated A.C. timings track so if one is a max. the other is probably a max., too?
A. It's true enough to usually give assurances, but we can only explicitly guarantee what's in the data sheet.


Q. Processor crashed, can't tell what happened.
A. Check for presence of ALE to see if the processor is running bus cycles. Apply HOLD and look for HLDA to see if the bus is idle.

Q. Old documentation is unclear on LOCK# on NMOS.
A. The C Stepping fixed LOCK# to be active throughout the bus cycle.

Q. NMOS 80186 hangs during back-to-back locked cycles.
A. This is the Sequential Locked Instructions Errata. Place some non-locked code between the locked instructions.

Q. Has the CMOS product ever had the Sequential Locked Instructions Errata?
A. No.

Q. On the devices with an 8-bit bus, what happens to address lines A15-A8?
A. They are active throughout the bus cycle.

Q. On I/O accesses, what happens on address lines A19-16?
A. The bus interface unit drives them to zero.

Q. Which bus cycles have highest priority?
A. DRAM refresh cycles have highest priority. See the 80C186 Hardware Reference Manual.

Q. Does ALE ever float?
A. ALE floats only in ONCE Mode. ALE is a well-behaved signal, staying low except to indicate a bus cycle.

Q. How important is the LOCK#/INTA Errata?
A. The LOCK#/INTA Errata does not affect systems with the 8259A, but it might affect systems with the 8274. We do not know of other extant devices which the LOCK#/INTA bug affects. The EX core-based products fix the LOCK#/INTA Errata.

Q. What about word operations on the 80C188?
A. The two bus cycles are inseparable and the BIU accesses the low byte first.

Q. On the NMOS 80186, BHE# does not go active on a DMA fetch from an odd address.
A. This is the BHE# During DMA Errata, seen sometimes above 8 MHz. See the errata sheet.

Q. If an interrupt is serviced during a WAIT instruction, will WAIT resume afterward?
A. Yes.

Q. Is ready used during a HALT bus cycle?
A. No.

Q. After a HLT instruction, is the bus turned completely off?
A. Not necessarily. Refresh, DMA, and HOLD can still work.

Q. What causes idle states on the bus?
A. Prefetch queue full, destination-sync. DMA, cycles after non-pipelined effective address, INTA cycles, and locked cycles.

Q. What happens to the DT/R# pin between bus cycles?
A. It doesn't change states if the next bus cycle is a like (both read or both write) cycle.

Q. What is the significance of the timing changes on the 80C186EB DEN# and DT/R# pins over the 80C186?
A. The new timings allow easier system design because DEN# and DT/R# cannot change on the same edge going from write cycle to read cycle.


Q. What are the default wait state assumptions at RESET?
A. UCS# is active for the top 1K of memory with the maximum number of programmable states.

Q. What is the default READY assumption at RESET?
A. External READY used.

Q. What is the default for areas not under a chip select?
A. 0 W.S., external ready used. Keep this in mind if you don't use the chip selects.

Q. When using the standard 80C186 I have a 256K MCS# block starting on at 64K (or similar).
A. Won't work. With the 186-style chip select unit, the starting address must be a multiple of the block size.

Q. When PCS5# and PCS6# are used for latched A1 and A2, what are the timings?
A. Same as for the chip selects.

Q. What happens to the MCS2# pin under 80C186 Enhanced Mode?
A. It retains its normal functionality. If MCS0#, MCS1#, and MCS3# pins are unavailable, what happens to the wait state/ready functionality?

Q. It is programmable just like before. Is it possible to wire-AND the chip-select outputs?
A. No. Only P2.7 and P2.6 of the 80C186EB have open-drain output drivers.

Q. Is it possible to overlap chip select regions?
A. Yes, but be careful on the 80C186/80C188 which doesn't have enhanced chip selects.

Q. Is it possible to overlap a chip select and the Peripheral Control Block?
A. No, under all circumstances.

Q. Is it possible to disable mid-range chip selects (186-style chip select unit)?
A. No. You need the 80C186EB or 80C186EC.

Q. Chip select outputs appear wrong on some parts.
A. Check programming for invalid combinations. The MCS# block size must be a multiple of the base address.

Q. I don't want to use external ready logic.
A. Tie at least one READY pin high.

Q. Unsure about external ready logic.
A. Serious problems can result if you violate setup and hold times for either the SRDY pin or the ARDY pin in a normally-ready configuration. Follow the manual carefully.

Q. Unsure about logic driving ready pins, Possible erratic operation ("old" 80C186 only).
A. On the "old" 80C186, the input high voltage is higher than other pins. Pullup resistors on the ready pins gives relief.

Q. Is there any maximum number of wait states?
A. If external ready is used, the answer is no.

Q. Are chip select lines glitch-free?
A. Yes. Take the A.C. timings as they are written.

Q. Do chip selects go inactive between accesses to the same region?
A. Yes.

Q. What is the purpose of having latched A1 and A2?
A. Certain older peripherals require it.

Q. The enhanced chip select unit only has 10 chip selects instead of the 13 on the original chip select unit.
A. Yes, but their vastly improved versatility compensates.


Q. How do you drive the CPU with a canned oscillator?
A. Connect it to the X1 or CLKIN inputs only, even if NMOS. Leave X2 N.C.

Q. Unsure about crystals.
A. Call a crystal manufacturer to obtain recommendations.

Q. Want to use crystal or capacitors different from recommendations.
A. Check startup carefully across expected temperature and voltage.

Q. Wanting to use a series-resonant crystal rather than parallel resonant.
A. Should work fine, but expect the frequency to be about 0.02% higher than stamped on the crystal.

Q. Is it possible to use ceramic resonators?
A. Yes.

Q. What are the guidelines on using ceramic resonators?
A. You may need to increase the capacitance at X1 and X2 slightly. Consult the vendor.

Q. How long is oscillator startup time?
A. Startup is on the order of a millisecond or less, inversely proportional to frequency.

Q. How fast does a third overtone crystal start up?
A. It starts up slower than a fundamental mode crystal of the same frequency.

Q. Crystal doesn't work right.
A. If it's a third overtone crystal, you must use an LC circuit to avoid fundamental mode oscillation.

Q. Where can I find the inductors mentioned for the third overtone crystal circuit?
A. Look for plastic molded or epoxy conformal coated models. Try Dale model IR-2 or Miller model 76F. Toko America and Dale make suitable surface-mount inductors.

Q. Why bother with third overtone crystals?
A. At higher frequencies, fundamental mode crystals are thin and fragile.

Q. When I buy crystals, when should I expect to get fundamental or third overtone?
A. Up to about 25 MHz, most crystals are fundamental. Above that, plan to get a third overtone xtal.

Q. The rise time specification for CLKIN appears too tight.
A. In general, you can use the fastest practical canned oscillator with a CMOS buffer and not worry.

Q. Can I use the oscillator output to drive other devices?
A. No.


Q. Device appears excessively noisy (Old 80C186).
A. Try the 80C186EB. Try the 80C186 in the 80-lead package. Use better board layout. Use bus termination; series resistance may offer some relief. Buffer large loads. Use a multi-layer board. Sockets increase noise.

Q. Can noisy 80C186 devices cause system failure?
A. It is very, very rare.

6. DMA

Q. What is the purpose of the DHLT bit?
A. It's there mostly for NMI to use to turn off the DMA.

Q. Problems with DRQ in source-synchronized mode.
A. The critical sampling edge is 4 clocks before the clock edge of the next possible transfer.

Q. Problems with DRQ in destination-synchronized mode.
A. The critical sampling edge is 4 clocks before the clock edge of the next possible transfer.

Q. If I float DRQ, what happens?
A. Nothing, unless DMA is turned on. However, power consumption may increase.

Q. DMA programmed for alternation but channels don't alternate.
A. Alternation is in effect only when both DRQ pins are simultaneously active.

Q. What happens if the SYN bits equal 11 binary?
A. We don't know. This is a reserved condition.

Q. What are the factors involved in DMA latency?
A. Consider non-pipelined EA cycles, refresh, HOLD, and interrupt vectoring sequences.

Q. Will interrupts choke off the DMA from the bus?
A. Yes. Interrupt vectoring sequences have higher priority.

Q. Can one use DMA to the Peripheral Control Block?
A. Not as of this writing.

Q. If NMI is received during DMA transfers, what happens?
A. The DMA transfer finishes before the NMI service starts.


Q. AP-186 says...
A. AP-186 is an obsolete document. See the User's Manual.

Q. Is there a reliability summary available?
A. Yes. Call 1-800-628-8686.

Q. What are the thermal coefficients (Thetas)?
A. Call 1-800-628-8686.

Q. What is the maximum allowable die temperature in a plastic packages?
A. The die temperature must not exceed 140 C.

Q. What is the maximum allowable die temperature in a ceramic package?
A. The die temperature must not exceed 150 C. Packaging: plastic mold compound, lead finish, dimensions. Call 1-800-628-8686.

Q. What is the gate count?
A. We provide transistor counts only. Call 1-800-628-8686.

Q. Which stepping is this part?
A. Check the last pages of the data sheet for stepping information.

Q. How do I return parts for failure analysis?
A. Call 1-800-628-8686.

Q. How do I specify bypass capacitors?
A. Try to get low inductance.

Q. Problems with military devices.
A. Contact the military operation for questions on military or space-qualified devices.

Q. Processor to be used in life support equipment.
A. Intel makes no particular stipulations for this application. Customers use the 80C186 with confidence in a variety of medical equipment.

Q. Which product family is Intel's all-time design win leader?
A. The 80C186 Embedded Microprocessor Family.


Q. Are there any limitations to the size of DRAMs which can be refreshed?
A. The "old" refresh unit can accommodate DRAMs with up to 9 cell rows. The "enhanced" refresh unit can accommodate DRAMs with up to 12 cell rows.

Q. What happens to A0 on an 8-bit device during DRAM refresh cycles?
A. It is a logic 1, just like as in the 16-bit bus versions. Don't connect it as a row address bit.

Q. What is the state of S6 during DRAM refresh cycles?
A. It is low.

Q. How does the processor handle refresh cycles when the bus is in HOLD?
A. The CPU lowers HLDA to signal to the external hardware its need to run the refresh.

Q. Are refresh requests queued?
A. No. If the CPU doesn't get the bus back before time to run still another refresh cycle, it loses the first refresh cycle (row address).

Q. Processor lowers HLDA to regain bus, then hangs.
A. See errata for Bus Preemption Problem.

Q. On the "old" 80C188, the RFSH# pin appears to work incorrectly.
A. This is an errata fixed in the "new" 80C188 and all EX core-based products.


Q. What is the approximate MIPs rating of the 80C186?
A. About 0.9 MIPs at 16 MHz.

Q. What is the approximate Dhrystone rating of the 80C186?
A. 2000 at 16 MHz.

Q. What happens when string instructions cross 64K boundaries?
A. The segment register does not rollover. The pointer wraps.

Q. Do you have 20 MHz?
A. Yes, but only on the "new" 80C186/80C188 and 80C186EA/80C188EA.

Q. How are instruction counts based?
A. The premise is that all the necessary bytes are in the prefetch queue at the start of the instruction.

Q. How do wait states affect overall performance?
A. It is not a linear relationship. One wait state will degrade performance about 15%.

Q. How accurate is adding the published clock counts?
A. Allow an extra 5-10% to account for idle states, queue flushes, etc.

Q. 80C188 gives about half the expected performance.
A. Many applications are very bus intensive and the bus width comes into play.

Q. On the 8-bit bus, what happens during word I/O instructions like OUTS?
A. The processor stuffs both bytes into the same I/O port address.


Q. Can HOLD separate bus cycle sequences?
A. Yes, unless locked, a non-pipelined effective address calculation, second part of odd-addressed pair, or DMA cycle pair.

Q. Can HOLD separate data cycles that are part of a numerics coprocessor instruction?
A. Yes.

Q. How does the CPU regain the bus to run a refresh cycle?
A. The CPU lowers HLDA. The system must release HOLD, else the refresh for one row gets lost.

Q. "Old" 80C186/80C188 hangs during arbitration for DRAM refresh.
A. Usually seen when using an external DMA controller. Read errata for Bus Preemption Problem and look at Tech Bit MIC-02 dated January 27, 1989 for workarounds.

Q. Bus Preemption Problem.
A. The workaround in the Tech Bit is correct, but enhancements may be needed to cover situations when the busis halted or running DMA.

Q. When will Intel fix the Bus Preemption Problem?
A. The EX core fixes the problem. Thus, the "new" 80C186 and all -EX derivatives automatically do not have the errata.

Q. Can NMI recover the bus when it's in HOLD?
A. No, there is no mechanism.

Q. Can the processor recognize HOLD in RESET?
A. Yes.

Q. How long must HOLD be removed to allow just one or two CPU bus cycles to squeeze through?
A. One clock, with the possible exception of the Bus Preemption Errata on the 80C186/80C188. See errata.


Q. Cascaded 8259A appears confused at powerup.
A. Be sure to put pullups on the INTA# lines because they are inputs until you program the cascading.

Q. Timing problems interfacing the 8259A.
A. Use faster 8259A from various manufacturers. The 8259A usually needs buffering and wait states (using external ready logic). Check address hold time carefully. Insert NOP(s) between back-to-back register accesses. Lock register accesses to satisfy RD#/WR# to INTA# time but be aware of the LOCK#/INTA Errata on some devices. Examine 8259A address hold timing carefully.


Q. When is an interrupt effective?
A. The processor recognizes it at the next instruction boundary.

Q. Is the interrupt table relocatable?
A. Sorry, the answer is no.

Q. Can INTA cycles break into the sequence of, say PUSHA?
A. No. Interrupt vectoring can only start when the instruction's bus cycles are over.

Q. How long must NMI remain active?
A. At least one clock.

Q. Can NMI interrupt itself?
A. Yes, it can nest repeatedly. Connect the NMI input carefully.

Q. Spurious NMI interrupts.
A. Protect the input line carefully from noise.

Q. When is the earliest the processor will recognize NMI?
A. On the trailing edge of the RESET input.

Q. What is the latest assertion time to get NMI before the first instruction?
A. 10 clocks following the inactive edge of the RESET input.

Q. Does NMI require an end-of-interrupt?
A. No. There is no in-service register.

Q. If an NMI request is received during HOLD, will the CPU recognize it?
A. Yes.

Q. If an interrupt input is floated, what happens?
A. Nothing, unless the pin is NMI or interrupts are enabled. However, power consumption may increase.

Q. Are interrupt requests latched?
A. Only internal requests and NMI. External requests on INT0-3 must be active until the vectoring sequence starts, even if edge-triggered.

Q. Once an interrupt vectoring sequence starts, what happens to prefetching?
A. As a lower priority, it stops.

Q. How can I tell when an interrupt is acknowledged when there isn't an external INTA# pulse?
A. Acknowledgement is the start of the vectoring sequence, indicated by reading the IP of the interrupt vector.

Q. How similar is an INTA cycle to a read cycle?
A. For signals like DEN# and DT/R#, it is identical. RD# does not go active.

Q. Not getting any hardware interrupts.
A. Did you execute the STI (set interrupt enable) instruction?

Q. What is the interrupt latency time?
A. Interrupt latency is the time to the next instruction edge, which can be extremely long.

Q. What is the interrupt response time?
A. 42 to 55 clocks for all products.

Q. What is the status of the LOCK#/INTA Errata?
A. The "new" 80C186/80C188, like other EX core devices, will not have it.

Q. Confused about Slave Mode.
A. Slave Mode places the processor's interrupt controller under the control of an external 8259A master. This feature allows the user to alter interrupt type numbers. It is rarely used anymore.

Q. What is the minimum low pulse for an edge-triggered interrupt?
A. One clock.

Q. Mysterious problems with edge-triggered or level-triggered operation.
A. Try the other mode. Often the problem will go away, or you will gain insight from the process.

Q. Is it necessary to provide READY for INTA cycles?
A. Yes.

Q. How is the interrupt vectoring sequence encoded on the status lines?
A. Just like other memory accesses.

Q. When does the pending bit change?
A. It sets when the in-service bit sets. Therefore, interrupts can only be "remembered" one deep.

Q. I have many interrupts I want to ignore.
A. Poll the poll register until INT REQ = 0. Perform an EOI each time.

Q. What is the purpose of performing an EOI?
A. EOI clears the in-service bit for a specific interrupt source. A non-specific EOI is useful for nested interrupts. Too many interrupts to take the time to perform EOIs. Try using the Special Fully Nested Mode.

Q. Does the 80C186 have a "spurious" interrupt like the 8259A?
A. No.


Q. What good are the unused registers?
A. They can be used for data storage.

Q. What is the importance of P2.6 and P2.7 on the 80C186EB?
A. Since they are open drain, you may use them to implement such interfaces as I2C.

Q. What is the RESET condition?
A. Port 1 is configured for chip selects. Port 2 is configured as a serial port with P2.6 and P2.7 in the high impedance state.


Q. What numerics processors are available?
A. For the NMOS, use only the 8087-10. The 80C187 works with selected packages of the 16-bit CMOS products.

Q. Does the 80C187 work with the 80C188 or other 8-bit bus versions?
A. No.

Q. What are the clock input limitations of the 80C187?
A. When using the 80C187 above 12.5 MHz, it must have its own oscillator. Don't use the 80C186 CLKOUT.

Q. What are the details of the interconnection of the 80C187 and the 80C186?
A. See the 80C187 data sheet.

Q. Is it possible for software to test the presence of the 80C187?
A. No. Without the coprocessor in place, the FNINIT and FNSTSW instructions used in the test will themselves fail. A hardware fix is available.

Q. Summarize the NMOS numerics interface.
A. It is synchronous, using an 82188 bus arbiter with the 8087 as a bus master.

Q. Summarize the CMOS numerics interface.
A. It is asynchronous. The 80C187 is a slave device with data flowing through four dedicated I/O ports.

Q. What performance improvement should the C187 provide over the 8087?
A. The performance increase results from increased frequency. At the same frequency, the performance is 0.9X to 1.2X.

Q. Difficult to troubleshoot transfers between the 80C186 and the 80C187.
A. The interface is proprietary. Call the factory if you need a detailed problem analysis.

Q. In a large system using the 80C187, what precautions should be taken?
A. The 80C187 should reside on the 80C186 side of any bus transceivers. Be certain to disable the transceivers during numerics accesses.


Q. Does Intel have setup and hold times for ONCE activation?
A. No. the enabling signal(s) are expected to be left grounded for an indefinite time.

Q. When the 80C186/80C188 enters ONCE, when do the pins float?
A. It depends on the set of pins in question. Contact the factory if you need to know.

Q. Does CLKOUT float in ONCE?
A. Yes.

Q. How can I connect to a QFP device soldered in place?
A. For ONCE, use an emulator with an"iron fist". Emulation Technology makes special probe clips, too.

Q. Trouble extracting PLCC devices from sockets.
A. Special extraction tools are readily available from Amp and probably others.


Q. Processor hangs.
A. Check ready logic to see if stuck in wait states. Check for uninitialized interrupt vectors.

Q. Board has problems at higher frequency.
A. Be more careful about layout and trace length. Protect oscillator, reset, and interrupt inputs from noise. Avoid wire-wrapped boards. Terminate long, loaded, and clock lines. Buffer large loads.

Q. Processor executing in never-never land.
A. Check for uninitialized interrupt vectors. Check for bad setup and hold timing on READY pin.

Q. Processor problems vary depending on instructions executed.
A. The problem is either random or dependent on the exact sequence of bus cycles. Instruction execution per se is trouble-free for this product family.


Q. Doing byte writes to the Peripheral Control Block.
A. All 16 bits will be affected. The 8-bit bus devices comprise a special case. See the User's Manual.

Q. On the 8-bit bus versions, how do I relocate the Peripheral Control Block?
A. Use a byte write, not a word write.


Q. What is the purpose of Idle Mode?
A. Idle Mode is useful when the design spends a lot of time waiting for, say, keyboard input.

Q. What is the purpose of Powerdown Mode?
A. Powerdown is useful when the processor will be idle for long periods and the oscillator startup time is not a problem when responding to inputs.

Q. What happens to the bus in Idle Mode?
A. It is frozen unless the processor must "wake up" temporarily to run refresh cycles. HOLD/HLDA will also "wake up" the device.

Q. How do I choose the powerdown capacitor?
A. Look at the oscillator startup on a scope and try several values until the processor wakes up well after oscillator startup.

Q. What happens to DRAM refresh with power management?
A. In Idle Mode, the CPU will wake up long enough to do programmed refresh cycles. In Powerdown Mode, the processor turns DRAM refresh off.


Q. When does the processor enter Power Save?
A. Power Save starts on the T3 phase of the write to the control register.

Q. When does the processor leave Power Save?
A. Power Save ends on a T3 phase also,but the exact bus cycle in progress at that time will vary.


Q. What is needed for a good RESET?
A. Vcc stable, oscillator startup, RESET input active.

Q. How long should the RESET input be active?
A. At least four clocks.

Q. How do you synchronize two processors in a fault-tolerant system?
A. Reset both together with critical attention to setup on the RESET input.

Q. What is the hysteresis on the 80C186 RESET pin?
A. It was characterized at 200-500 mV but is not tested. If RESET signal is questionable, use an external Schmitt trigger. This is particularly necessary on the A Stepping of the 80C186EB.

Q. Not getting clean RESETs.
A. Check carefully over temperature and voltage. If -EB or XL, provide hysteresis externally and see errata. If a critical design, use a power monitor such as a Dallas Semiconductor model. Such devices are widely used in 80C186 designs.

Q. For RC RESET input, what should be the RC constant?
A. Aim for about 100 ms.

Q. On a warm RESET, does the instruction in progress finish?
A. No. Reset is not synchronized to an instruction edge.

Q. On a warm RESET, which registers retain their states?
A. Assume that none of them do.

Q. When are pins first driven after RESET?
A. The first fetch is just like coming out of a HOLD state.

Q. How strong are the active pullups on the 80C186 at RESET?
A. In one experiment, they looked like resistors with a value 1.2K +/- 33%.


Q. What is the maximum data transfer rate of the serial unit?
A. 1/16 the processor clock.

Q. What is the performance limit of the serial channel?
A. The serial unit is limited only by how fast the CPU can service it.

Q. What is Mode 0 used for?
A. Mode 0 is 8-bit and synchronous. It is useful to communicate with shift register like devices.

Q. What is Mode 1 used for?
A. Mode 1 is for standard 7-or 8-bit asynchronous communication.

Q. What is Mode 2 used for?
A. Mode 2 is the 8-bit plus addressing bit mode. It is useful for inter-processor communication.

Q. What is Mode 3 used for?
A. Mode 3 is similar to Mode 2 but the 9th bit is for data or parity.

Q. What is Mode 4 used for?
A. Certain older serial devices use Mode 4, a 7-bit mode.

Q. SINT1 pin on 80C186EB not latched.
A. The B Stepping fixes the errata.


Q. Who makes relatively low cost real-time kernels?
A. Try JMI Software, Byte-BOS, and Accelerated Technology, among others.

Q. Are code converters available for Z-80 and 8085 code?
A. Yes. Call the Applications BBS at (916) 356-3600.


Q. Timers 0 and 1 don't count on internal clock.
A. You must tie the input pins high.

Q. Timers appear to count wrong after RESET.
A. Be sure to initialize all timer registers, even the count register.

Q. How fast can the timers count?
A. Events happening more often than once every 4 clocks are subject to getting missed.

Q. What is the minimum high time on a time input?
A. One clock.

Q. Can Timer 2 prescale Timer 1 and give timed DMA requests, too?
A. Yes.

Q. When a timer times out and stops, what is the state of the output pin?
A. High.

Q. Unexplained timer problems.
A. Check the clock input to the processor.


Q. What are the valid part numbers for the 186 evaluation boards?
A. EV80C186EAXL, EV80C186EB, EV80C186EC

Q. Are there any design kits available for the 80C186xx ?
A. Yes, Intel offers design kits by Paradigm and Microsoft/SSI.

Paradigm Design Kits:  

Q. What is included in the Paradigm Design Kit?
A. The Paradigm Design Kit combines one of Intel's 186 evaluation boards with the Paradigm DEBUG/RT enhanced Turbo Debugger, Paradigm LOCATE, and TDREM a turbo debugger remote interface.

Q. What is included in the Microsoft/SSI Design Kit?
A. This design kit includes one of Intel's 186 evaluation boards, the Microsoft C/C++ compiler and Windows SDK, the CV/RTD 86 remote target debugger with a nonreconfigurable remote monitor, and CV/Link the CodeView compatible absolute linker and locator

Q. What are the features of the 80C186xx evaluation board?
A. Refer to FaxBACK documents

2085	Fact Sheet on the EV80C186EB Evaluation Board 
2143	Fact Sheet on the EV80C186EC Evaluation Board  
2084	Fact Sheet on the EV80C186EA/XL Evaluation Board 
Q. How can I get the schematics for the evaluation boards?
A. The schematics are available at this site under Intel Architecture/Use/80186 Enhanced/Design Info/Schematics:
	EV186EB.ZIP  Schematics for the 186EB  
	EV186EA.EXE  Schematics for the EA/XL
Q. Is there an evaluation board available for the 80C188xx ?
A. The EV80C186XX boards do support the 188 processors. To use a 188 processor in the 186evaluation boards you need to:
1. 	Replace the 186 processor with the 188 processor.   
	Part Numbers for the 188 processors are as follows:   
		186EA/XL Evaluation Board		N80C188EA-25 or N80C188XL   
		186EB Evaluation Board			N80C188EB-25   
		186EC Evaluation Board			KU80C188EC-25  
2. 	Switch the Dip Switch on the Evaluation Board to the 8bit position.  
3. 	If you have the EV80C186EB, the DK80C186EB or the DKCV80C186EB 
	you must also remove U25 when using the board with the N80C188EB-25 processor. 
Q. What file format do the evaluation boards accept?
A. The Intel evaluation board uses the Intel OMF file format. The evaluation board does not accept executable files because they are relocatable and are intended for use in Operating System environments like DOS. If need to use an executable file, first run it through a relocator to make an absolutely located file which the evaluation board will accept. Paradigm and SSI offer locators that can be configured to generate Intel OMF files.

Q. Is there any errata on the 186 family Evaluation Boards?
A. Yes, there is some known errata associated with the evaluation boards, Refer to FaxBACK document #2592.

Q. Having problems using the Expansion bus on the 186EA/XL or 186EC evaluation board, is there any errata associated with this?
A. Yes, there is an incorrect PLD equation which prohibits reads from the Expansion bus. Refer to FaxBACK document #2592 for the correct PLD equation.

Q. Having DRAM Refresh problems on the 186EC evaluation board, is there any errata associated with this?
A. Yes, in the RISM monitor, the DRAM Refresh Base Address register is programmed incorrectly. The DRAM base address is set to 0000H and the DRAM chip select is never activated, therefore the DRAM is never being refreshed. (Note: This does not affect boards using the Paradigm Software). Refer to FaxBACK document #2592 for the possible fixes.

Q. Where can I find the RISM code for the evaluation boards?
A. The RISM code is available on BBS system (916-356-3600). File names are as follows:

File Name  
Q. What else do I need to run the evaluation board?

1. Power Supply (connector included w/ eval board purchase)
2. IBM PC Compatible Computer
3. Straight Through Serial Cable

Q. What are the I/O addresses of the LEDs and Dip Switches?
Eval Board	LED Address		Dip Switch Address  
186XL/EA	488H ( Bar display LEDs) 	484H  
186EB		P1.0-3				110H  
186EC		1000H (7-segment LEDs)		1030H
Q. What processor comes with the EV80C186EAXL evaluation board?
A. The 186EA processor comes with the EV80C186EAXL.

Q. What are the literature numbers for the evaluation board user's manuals?
A. The literature numbers are as follows:

EV80C186EA/XL User's Manual 	272124
EV80C186EB User's Manual	272068
EV80C186EC User's Manual	272125 

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